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AgeCommit message (Expand)AuthorFilesLines
2018-10-29Tweak debug tests to run out of flash.Tim Newsome4-8/+17
2018-10-24Merge branch 'TriggerLoadAddressInstant'Tim Newsome1-12/+1
2018-10-24Re-enable TriggerStoreAddressInstantTim Newsome1-12/+1
2018-10-05Make HwWatchpoint test fail on incorrect result.hw_watchpointTim Newsome3-7/+10
2018-10-03Added tests for hw and sw watchpointscgsfv3-0/+88
2018-09-23bump envAndrew Waterman1-5/+5
2018-09-13Assert if HiFive1 program is too large.Tim Newsome1-0/+2
2018-09-13Put debug test stack in data instead of textTim Newsome1-0/+1
2018-09-08Merge branch 'tommythorn-master'Andrew Waterman6-0/+42
2018-09-08RV64 s{ll,ra,rl}w tests with non-canonical valuesTommy Thorn6-0/+42
2018-09-06Revert "breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) ...Andrew Waterman1-1/+1
2018-09-06breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) (#159)Tommy Thorn1-1/+1
2018-09-03Merge pull request #156 from riscv/PrivChangeTim Newsome1-27/+26
2018-08-31Fix CustomRegisterTest.Tim Newsome2-5/+6
2018-08-29Add test case for `riscv expose_custom`.Tim Newsome12-0/+55
2018-08-28Reset address translation/perms before PrivChangeTim Newsome1-27/+26
2018-08-27Neuter TriggerStoreAddressInstantTim Newsome1-1/+13
2018-08-27Make pylint happy.Tim Newsome1-1/+2
2018-08-25Temporarily disabling PrivChange testAndrew Waterman1-22/+23
2018-08-23Make pylint happy with change d1d2d953b5016b465.Tim Newsome2-3/+4
2018-08-23Get all of the log into the final log fileTim Newsome1-6/+20
2018-08-23Merge pull request #153 from dmitryryzhov/rtos-switch-active-threadTim Newsome1-0/+28
2018-08-22Merge branch 'master' of https://github.com/riscv/riscv-testsTim Newsome1-2/+2
2018-08-22Disable MulticoreRunHaltStepiTestTim Newsome1-52/+52
2018-08-22Add debug test, which checks that openocd correctly switch active thread on a...Dmitry Ryzhov1-0/+28
2018-08-21Changing the register mstatus is read into (#152)Srivatsa Yogendra1-2/+2
2018-08-20Revert "Fix to solve the failing tests shamt, csr and scall (#151)"Andrew Waterman2-52/+5
2018-08-17Fix to solve the failing tests shamt, csr and scall (#151)Srivatsa Yogendra2-5/+52
2018-08-17making mtvec_handler global (#150)Srivatsa Yogendra1-0/+1
2018-08-13Add jump/hbreak test.Tim Newsome1-0/+23
2018-07-09Check that SC yields the load reservationAndrew Waterman1-0/+9
2018-07-03rwatch/watch on explicit addressTim Newsome1-2/+4
2018-06-18Add reproduce line to the end of debug test logsTim Newsome1-0/+2
2018-05-21Merge pull request #141 from riscv/mrhstestTim Newsome2-23/+46
2018-05-18Fix MulticoreRunHaltStepiTestTim Newsome2-23/+46
2018-05-15Merge pull request #139 from riscv/debug-tests-more-singleMegan Wachs2-10/+19
2018-05-14Merge remote-tracking branch 'origin/downloadtest' into debug-tests-more-singleMegan Wachs2-21/+11
2018-05-14Make DownloadTest properly park other harts.Tim Newsome2-5/+9
2018-05-14debug: remove some unintentionally added newlinesMegan Wachs1-2/+0
2018-05-14debug: Fixing the non-RTOS behavior for DownloadTestMegan Wachs1-7/+16
2018-05-11debug: mark more tests as single-hart testsMegan Wachs1-6/+13
2018-05-11debug: output some more useful info into the post-mortem dataMegan Wachs1-0/+5
2018-04-30[rv64ua/lrsc] Initialize memory read out. (#135)Christopher Celio1-1/+3
2018-04-30Fix formatting to make pylint happy.Tim Newsome1-5/+6
2018-04-28Merge pull request #132 from riscv/debug-clear-satpMegan Wachs1-0/+7
2018-04-27debug: need to clear satp before changing privdebug-clear-satpMegan Wachs1-0/+7
2018-04-27Merge pull request #125 from riscv/debug-delete-simMegan Wachs1-17/+0
2018-04-27Merge pull request #130 from riscv/trap_entry_align-1Megan Wachs1-0/+1
2018-04-27debug: add missing align directive on trap_entrytrap_entry_align-1Megan Wachs1-0/+1
2018-04-24Fix race when making logs directoryTim Newsome1-1/+5
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