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AgeCommit message (Expand)AuthorFilesLines
2017-08-07rv64[ms]i-csr: Only emit F instructions when compiled for F.Richard Xia1-1/+6
2017-08-04RV32 div tests should use -2^31 for min value, not -2^63Andrew Waterman3-9/+9
2017-08-04Improve RVC testAndrew Waterman3-9/+9
2017-07-31Fix the end of MulticoreTest.Tim Newsome1-30/+22
2017-07-27Make pylint happy.Tim Newsome1-2/+2
2017-07-26Use new OpenOCD messages to determine gdb port.Tim Newsome1-41/+8
2017-07-21Only clean up logfiles that we know we created.Tim Newsome1-1/+1
2017-07-20Add back code to clean up triggers in entry.STim Newsome3-0/+24
2017-07-18Check all PCs after reset.Tim Newsome1-1/+7
2017-07-12Print out logs in more failure cases.Tim Newsome1-4/+10
2017-07-06Merge pull request #58 from riscv/fpga_reset_haltTim Newsome1-0/+5
2017-07-06debug: Make the 'out of reset' tests actually apply resetmwachs51-0/+5
2017-07-03Add gdb_setup to target for arbitrary gdb commandsTim Newsome2-0/+7
2017-07-03Don't clear triggers during execution.Tim Newsome1-9/+0
2017-06-27Tolerate missing misa register.Tim Newsome1-1/+7
2017-06-27Merge pull request #55 from riscv/debugTim Newsome1-1/+1
2017-06-27Merge pull request #56 from riscv/configTim Newsome26-284/+184
2017-06-26Move target definition into individual files.Tim Newsome26-284/+184
2017-06-23Test gdb/OpenOCD during regular test run.Tim Newsome1-1/+1
2017-06-22Add basic multicore test.Tim Newsome3-42/+128
2017-06-20Smoketest multicore.Tim Newsome3-14/+55
2017-06-19Write OpenOCD log when it crashes early.Tim Newsome1-2/+4
2017-06-16Store logs for all tests in logs/Tim Newsome1-30/+58
2017-06-15Test 64-bit addressing.Tim Newsome8-29/+90
2017-06-09Add final echo to E300/U500 OpenOCD scriptsTim Newsome2-0/+2
2017-06-09Make HiFive1 testing (mostly) work againTim Newsome2-2/+5
2017-06-09Fix using defaults for --server_cmd and --sim_cmdTim Newsome1-1/+1
2017-06-09Default to openocd, not riscv-openocdTim Newsome1-1/+1
2017-06-05Make pylint happy.Tim Newsome3-10/+13
2017-05-25Merge pull request #53 from richardxia/fail-if-simulator-exits-earlyPalmer Dabbelt1-0/+6
2017-05-23Fail if simulator exits early.Richard Xia1-0/+6
2017-05-22minNum -> minimumNumberAndrew Waterman2-4/+16
2017-05-18Merge pull request #52 from riscv/vcs_sim_cmdMegan Wachs1-1/+1
2017-05-18debug: Correct the calling for a 32-bit simulation targetMegan Wachs1-1/+1
2017-05-17Manually assemble bad shift amount, since assembler rejectsAndrew Waterman1-1/+1
2017-05-17Shorten the debug testsPalmer Dabbelt1-4/+4
2017-05-17Merge pull request #49 from riscv/no_examine_targetPalmer Dabbelt1-1/+10
2017-05-17Show the debug logs to stdout, to avoid travis timeoutsPalmer Dabbelt1-1/+1
2017-05-16debug: remove unused auto_int functionMegan Wachs1-3/+0
2017-05-16debug: Allow skipping the ExamineTarget task.Megan Wachs1-4/+9
2017-05-16debug: Allow skipping the ExamineTarget step by specifying misaMegan Wachs1-1/+8
2017-05-16Merge pull request #47 from riscv/debug-0.13Palmer Dabbelt21-188/+291
2017-05-16Change Spike's RAM location to match the linker scriptPalmer Dabbelt1-2/+2
2017-05-16Link the infinate loop at 0x10000000Palmer Dabbelt3-1/+3
2017-05-16Link in encoding.h instead of providing a path to itPalmer Dabbelt5-4/+5
2017-05-16debug: Update OpenOCD configs.Megan Wachs2-5/+4
2017-05-15Copy debug/programs to the build dir, so debug-check runsPalmer Dabbelt1-1/+2
2017-05-15Merge pull request #48 from riscv/testsPalmer Dabbelt4-106/+117
2017-05-15Disable another PRIV mention, for nowPalmer Dabbelt1-1/+2
2017-05-15Disable the tests that touch PRIV, it's not implemented yetPalmer Dabbelt1-62/+63
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