| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2018-02-27 | Test debug authentication.debug_auth | Tim Newsome | 4 | -3/+19 | |
| Also halt instead of reset spike targets, which tests a more complicated code path. | |||||
| 2018-02-09 | Test resuming from a trigger.resume_from_trigger | Tim Newsome | 3 | -10/+9 | |
| 2018-02-07 | Link scripts shouldn't be executable. | Tim Newsome | 1 | -0/+0 | |
| 2018-01-08 | Deal with gdb reporting pmpcfg0 not existing. | Tim Newsome | 2 | -3/+16 | |
| It's an optional register. | |||||
| 2018-01-05 | Add test for multicore failure | Tim Newsome | 2 | -5/+40 | |
| Specifically, make sure that after resuming all cores, and halting core 0, that OpenOCD's poll() doesn't mess up the currently selected hart to the point where memory accesses intended for core 0 go to core 1. | |||||
| 2018-01-02 | Test access exception behavior for illegal addresses (#111) | Andrew Waterman | 2 | -0/+71 | |
| OK'd by @palmer-dabbelt | |||||
| 2017-12-27 | Test FPRs that aren't XLEN in size. | Tim Newsome | 6 | -8/+20 | |
| Cover all combinations of 32,64 bit XLEN with F and FD extensions. Finishes Issue https://github.com/riscv/riscv-openocd/issues/110 | |||||
| 2017-12-21 | Add all-tests target. | Tim Newsome | 1 | -1/+3 | |
| I hope to use this in riscv-tools' regression.sh. | |||||
| 2017-12-21 | Merge pull request #110 from riscv/bump_env | Megan Wachs | 1 | -5/+5 | |
| tests: bump env to pick up new names for CSRs | |||||
| 2017-12-21 | tests: bump env to pick up new names for CSRs | Megan Wachs | 1 | -5/+5 | |
| 2017-12-20 | Remove `set arch riscv:rv%d` | Tim Newsome | 1 | -1/+0 | |
| gdb gets target XLEN from register width now, so this is taken care of automatically. | |||||
| 2017-12-20 | Verify that F18 does not exist on FPU-less targets | Tim Newsome | 1 | -17/+20 | |
| 2017-12-12 | Display env variables used when invoking OpenOCD | Tim Newsome | 2 | -6/+11 | |
| This makes it a little easier to just cut and paste from the log when reproducing a failure. (The port number still needs changing though.) | |||||
| 2017-12-01 | Ensure there are no unnamed registers. | Tim Newsome | 1 | -0/+2 | |
| 2017-11-30 | Merge pull request #109 from riscv/vcssim | Tim Newsome | 1 | -2/+12 | |
| Clean up VcsSim init() | |||||
| 2017-11-30 | Clean up VcsSim init() | Tim Newsome | 1 | -2/+12 | |
| Use a unique log file, so you can run multiple instances at once. Add time out to waiting for the simulator to be ready. | |||||
| 2017-11-27 | Rename sbadaddr to satp | Andrew Waterman | 5 | -14/+14 | |
| 2017-11-26 | Rv32ud tests (#108) | Torbjørn | 23 | -0/+318 | |
| * Probably implemented the changes required to support fadd test for rv32ud * Created test files in rv32ud, implemented working(?) test for ldst * fclass, fcvt_w, fmin and recoding seem to be working now * Got fdiv (and sqrt) tests working * fmadd tests seem to work * fcmp works * [WIP] fcvt working, but lacks a 32-bit implementation of the final test * Renamed macro TEST_LDST_D32 to TEST_CASE_D32 to indicate that it can be used for more than just LDST * Added Makefrag for rv32ud tests and included in main isa Makefile * Don't run 64-bit tests if the defined XLEN is 32 | |||||
| 2017-11-22 | Check sepc for rv64si/scall test. (#107) | Christopher Celio | 1 | -0/+4 | |
| Closes #105. | |||||
| 2017-11-20 | Check mtval in rv64mi-p-illegal (#104) | Andrew Waterman | 1 | -0/+11 | |
| Closes #103 | |||||
| 2017-11-19 | Ensure log file is fully written before reading it | Tim Newsome | 1 | -0/+1 | |
| Fixes --print-failures sometimes not actually printing out details about failures. | |||||
| 2017-11-19 | Make pylint happy. | Tim Newsome | 3 | -12/+16 | |
| 2017-11-17 | Merge pull request #102 from riscv/xlen_fix | Megan Wachs | 1 | -7/+8 | |
| debug: Fix the XLEN command line check | |||||
| 2017-11-17 | debug: Fix the XLEN command line checkxlen_fix | Megan Wachs | 1 | -7/+8 | |
| 2017-11-16 | Debug: Use the --32 and --64 command line arguments (#97) | Megan Wachs | 3 | -10/+17 | |
| * Debug: Actually use the --32 and --64 command line arguments * debug: make XLEN mismatch message clearer | |||||
| 2017-11-16 | Disable PMP for PrivRw test. | Tim Newsome | 1 | -0/+5 | |
| 2017-11-15 | Clarify PrivTest detail. | Tim Newsome | 1 | -0/+2 | |
| 2017-11-11 | Make sure that code is 4-byte aligned before disabling rvc (#100) | Andrew Waterman | 4 | -1/+5 | |
| 2017-11-09 | Make rv64mi-p-ecall work when U-mode is not present | Andrew Waterman | 1 | -1/+17 | |
| 2017-11-09 | Use mstatus.MPP to check existence of U-mode | Andrew Waterman | 1 | -5/+6 | |
| misa is allowed to be hardwired to 0, so checking its U bit could incorrectly suggest that U-mode is not supported. | |||||
| 2017-11-02 | Add --print-log-names to print temp log names ASAP | Tim Newsome | 2 | -5/+17 | |
| When not passed, they are no longer printed out. | |||||
| 2017-11-02 | Ensure gdb connection failures end up in main log. | Tim Newsome | 1 | -9/+18 | |
| 2017-11-02 | debug: Need to apply remotetimeout before connecting to remote target (#94) | Megan Wachs | 1 | -6/+7 | |
| * debug: Need to apply remotetimeout before connecting to remote target * debug: whitespace cleanup | |||||
| 2017-11-01 | SBREAK test now checks EPC value. (#92) | Christopher Celio | 1 | -0/+4 | |
| Closes #89 | |||||
| 2017-11-01 | Make pylint 1.6.5 happy. | Tim Newsome | 4 | -6/+5 | |
| 2017-11-01 | Test register aliases in the simple register tests | Tim Newsome | 1 | -9/+17 | |
| 2017-11-01 | Fix MulticoreRegTest. | Tim Newsome | 2 | -59/+65 | |
| This test would fail intermittently if gdb on the first hart managed to set a breakpoint, resume, halt, and clear the breakpoint before the second hart got a chance to resume. | |||||
| 2017-10-31 | Merge pull request #90 from richardxia/comment-out-multicore-reg-test | Palmer Dabbelt | 1 | -57/+58 | |
| Temporarily comment out MulticoreRegTest due to flakiness. | |||||
| 2017-10-31 | Temporarily comment out MulticoreRegTest due to flakiness. | Richard Xia | 1 | -57/+58 | |
| 2017-10-30 | Remove cache miss test from last AMO test. (#88) | Richard Xia | 1 | -17/+0 | |
| Follow-up to b68b39031a730ecc155ed87fba2ed5f111d0ab07. The 64KiB allocated by the code to force a cache miss makes it impossible to run the test from any memories that are smaller 64KiB, such as scratchpad memories or LIMs. Since this is trying to test microarchitectural behavior, they don't belong in these ISA tests anyway. | |||||
| 2017-10-30 | Declare trap handlers as global symbols. (#87) | Richard Xia | 8 | -0/+9 | |
| This allows them to be referenced by other files, such as a test environment that lives in a separate compilation unit. | |||||
| 2017-10-26 | Verify that mtval/stval is written correctly on misaligned fetch | Andrew Waterman | 1 | -1/+9 | |
| 2017-10-26 | Fix rv64mi-csr for the case where U-mode is not available. (#86) | Richard Xia | 1 | -0/+16 | |
| 2017-10-24 | Increase dual-core RV64 timeouts. | Tim Newsome | 2 | -2/+2 | |
| I need this for CompareSections to pass when I instrument spike to be really slow. | |||||
| 2017-10-19 | Get helpful gdb output in MemTestBlock. | Tim Newsome | 1 | -1/+4 | |
| 2017-10-12 | Pay attention to server_timeout_sec | Tim Newsome | 1 | -2/+3 | |
| Fixes #83. | |||||
| 2017-10-04 | Resurrect priv tests. | Tim Newsome | 1 | -52/+51 | |
| 2017-10-04 | Merge pull request #79 from riscv/multigdb | Tim Newsome | 13 | -96/+236 | |
| Multigdb support | |||||
| 2017-09-29 | Make ExamineTarget multi-core aware. | Tim Newsome | 1 | -18/+23 | |
| Now on multi-core targets it only runs once, wasting less time. | |||||
| 2017-09-29 | Fix tests to work in multi-gdb mode. | Tim Newsome | 13 | -87/+236 | |
| The Gdb class now can handle connecting to more than one gdb. It enumerates the harts across all connections, and when asked to select a hart, it transparently sends future gdb commands to the correct instance. Multicore tests still have to be aware of some differences. The main one is that when executing 'c' in RTOS mode, all harts resume, while in multi-gdb mode only the current one resumes. Additionally, gdb doesn't set breakpoints until 'c' is issued, so the hart where breakpoints are set needs to be resumed before other harts might see them. | |||||
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index : rocket-tools/riscv-tests.git | |
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