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rocket-tools/riscv-tests.git
attempt-travis-fix
ceasetest2
compliance_tests
cs152-sp18-lab3
debug
debug-0.13
debug-clear-satp
debug-delete-sim
debug_auth
debug_disassemble
disable_unavailable
dma-memcpy
eos20-bringup
hw_watchpoint
interrupts
master
misc
no_progbuf
priv
privchange-dontdeleteme
python3
rekall
resume_from_trigger
riscv-tests-sail
rtos
rvt-master
smi-demo
split-isa-tests
sqrt-171
tmp
trap_entry_align
trap_entry_align-1
travis-dev
trigger_priority
usb_error
xlen_fix
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2017-07-20
Add back code to clean up triggers in entry.S
Tim Newsome
3
-0
/
+24
2017-07-18
Check all PCs after reset.
Tim Newsome
1
-1
/
+7
2017-07-12
Print out logs in more failure cases.
Tim Newsome
1
-4
/
+10
2017-07-06
Merge pull request #58 from riscv/fpga_reset_halt
Tim Newsome
1
-0
/
+5
2017-07-06
debug: Make the 'out of reset' tests actually apply reset
mwachs5
1
-0
/
+5
2017-07-03
Add gdb_setup to target for arbitrary gdb commands
Tim Newsome
2
-0
/
+7
2017-07-03
Don't clear triggers during execution.
Tim Newsome
1
-9
/
+0
2017-06-27
Tolerate missing misa register.
Tim Newsome
1
-1
/
+7
2017-06-27
Merge pull request #55 from riscv/debug
Tim Newsome
1
-1
/
+1
2017-06-27
Merge pull request #56 from riscv/config
Tim Newsome
26
-284
/
+184
2017-06-26
Move target definition into individual files.
Tim Newsome
26
-284
/
+184
2017-06-23
Test gdb/OpenOCD during regular test run.
Tim Newsome
1
-1
/
+1
2017-06-22
Add basic multicore test.
Tim Newsome
3
-42
/
+128
2017-06-20
Smoketest multicore.
Tim Newsome
3
-14
/
+55
2017-06-19
Write OpenOCD log when it crashes early.
Tim Newsome
1
-2
/
+4
2017-06-16
Store logs for all tests in logs/
Tim Newsome
1
-30
/
+58
2017-06-15
Test 64-bit addressing.
Tim Newsome
8
-29
/
+90
2017-06-09
Add final echo to E300/U500 OpenOCD scripts
Tim Newsome
2
-0
/
+2
2017-06-09
Make HiFive1 testing (mostly) work again
Tim Newsome
2
-2
/
+5
2017-06-09
Fix using defaults for --server_cmd and --sim_cmd
Tim Newsome
1
-1
/
+1
2017-06-09
Default to openocd, not riscv-openocd
Tim Newsome
1
-1
/
+1
2017-06-05
Make pylint happy.
Tim Newsome
3
-10
/
+13
2017-05-25
Merge pull request #53 from richardxia/fail-if-simulator-exits-early
Palmer Dabbelt
1
-0
/
+6
2017-05-23
Fail if simulator exits early.
Richard Xia
1
-0
/
+6
2017-05-22
minNum -> minimumNumber
Andrew Waterman
2
-4
/
+16
2017-05-18
Merge pull request #52 from riscv/vcs_sim_cmd
Megan Wachs
1
-1
/
+1
2017-05-18
debug: Correct the calling for a 32-bit simulation target
Megan Wachs
1
-1
/
+1
2017-05-17
Manually assemble bad shift amount, since assembler rejects
Andrew Waterman
1
-1
/
+1
2017-05-17
Shorten the debug tests
Palmer Dabbelt
1
-4
/
+4
2017-05-17
Merge pull request #49 from riscv/no_examine_target
Palmer Dabbelt
1
-1
/
+10
2017-05-17
Show the debug logs to stdout, to avoid travis timeouts
Palmer Dabbelt
1
-1
/
+1
2017-05-16
debug: remove unused auto_int function
Megan Wachs
1
-3
/
+0
2017-05-16
debug: Allow skipping the ExamineTarget task.
Megan Wachs
1
-4
/
+9
2017-05-16
debug: Allow skipping the ExamineTarget step by specifying misa
Megan Wachs
1
-1
/
+8
2017-05-16
Merge pull request #47 from riscv/debug-0.13
Palmer Dabbelt
21
-188
/
+291
2017-05-16
Change Spike's RAM location to match the linker script
Palmer Dabbelt
1
-2
/
+2
2017-05-16
Link the infinate loop at 0x10000000
Palmer Dabbelt
3
-1
/
+3
2017-05-16
Link in encoding.h instead of providing a path to it
Palmer Dabbelt
5
-4
/
+5
2017-05-16
debug: Update OpenOCD configs.
Megan Wachs
2
-5
/
+4
2017-05-15
Copy debug/programs to the build dir, so debug-check runs
Palmer Dabbelt
1
-1
/
+2
2017-05-15
Merge pull request #48 from riscv/tests
Palmer Dabbelt
4
-106
/
+117
2017-05-15
Disable another PRIV mention, for now
Palmer Dabbelt
1
-1
/
+2
2017-05-15
Disable the tests that touch PRIV, it's not implemented yet
Palmer Dabbelt
1
-62
/
+63
2017-05-15
Have the openocd invocation match the spike invocation
Palmer Dabbelt
1
-1
/
+1
2017-05-15
Disable some failing tests for now
Palmer Dabbelt
1
-37
/
+40
2017-05-15
Don't rely on Spike's default ISA
Palmer Dabbelt
1
-1
/
+3
2017-05-15
Don't use the RTOS, and do "reset halt"
Palmer Dabbelt
1
-3
/
+4
2017-05-15
Let Spike have the default amount of RAM
Palmer Dabbelt
1
-1
/
+0
2017-05-15
Don't build openocd here, it's in riscv-tools now
Palmer Dabbelt
1
-1
/
+5
2017-05-15
debug: fix the make target for debug-check
Megan Wachs
1
-19
/
+2
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