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-rw-r--r--debug/testlib.py5
1 files changed, 3 insertions, 2 deletions
diff --git a/debug/testlib.py b/debug/testlib.py
index 64c7055..0279b08 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -137,6 +137,9 @@ class Spike:
else:
isa = f"RV{self.harts[0].xlen}G"
+ if 'V' in isa[2:]:
+ isa += f"_Zvl{self.vlen}b_Zve{self.elen}d"
+
cmd += ["--isa", isa]
cmd += ["--dm-auth"]
@@ -162,8 +165,6 @@ class Spike:
if not self.support_haltgroups:
cmd.append("--dm-no-halt-groups")
- if 'V' in isa[2:]:
- cmd.append(f"--varch=vlen:{self.vlen},elen:{self.elen}")
assert len(set(t.ram for t in self.harts)) == 1, \
"All spike harts must have the same RAM layout"