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-rw-r--r--debug/targets/RISC-V/spike32-2.py2
-rw-r--r--debug/targets/RISC-V/spike32.py3
-rw-r--r--debug/targets/RISC-V/spike64-2.py2
-rw-r--r--debug/targets/RISC-V/spike64.py3
4 files changed, 6 insertions, 4 deletions
diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py
index 719009d..f57f816 100644
--- a/debug/targets/RISC-V/spike32-2.py
+++ b/debug/targets/RISC-V/spike32-2.py
@@ -9,4 +9,4 @@ class spike32_2(targets.Target):
timeout_sec = 30
def create(self):
- return testlib.Spike(self)
+ return testlib.Spike(self, isa="RV32IMAFC")
diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py
index 809463c..dfcfc01 100644
--- a/debug/targets/RISC-V/spike32.py
+++ b/debug/targets/RISC-V/spike32.py
@@ -15,4 +15,5 @@ class spike32(targets.Target):
timeout_sec = 30
def create(self):
- return testlib.Spike(self)
+ # 64-bit FPRs on 32-bit target
+ return testlib.Spike(self, isa="RV32IMAFDC")
diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py
index 79aab3e..a2082b4 100644
--- a/debug/targets/RISC-V/spike64-2.py
+++ b/debug/targets/RISC-V/spike64-2.py
@@ -9,4 +9,4 @@ class spike64_2(targets.Target):
timeout_sec = 60
def create(self):
- return testlib.Spike(self)
+ return testlib.Spike(self, isa="RV64IMAFD")
diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py
index 2cd67a5..2aa1dd0 100644
--- a/debug/targets/RISC-V/spike64.py
+++ b/debug/targets/RISC-V/spike64.py
@@ -15,4 +15,5 @@ class spike64(targets.Target):
timeout_sec = 30
def create(self):
- return testlib.Spike(self)
+ # 32-bit FPRs only
+ return testlib.Spike(self, isa="RV64IMAFC")