diff options
| -rwxr-xr-x | debug/programs/entry.S | 15 | ||||
| -rw-r--r-- | debug/programs/mprv.S | 4 | ||||
| -rw-r--r-- | debug/targets/HiFive1/openocd.cfg | 2 | ||||
| -rw-r--r-- | debug/targets/freedom-e300-sim/openocd.cfg | 2 | ||||
| -rw-r--r-- | debug/targets/freedom-e300/openocd.cfg | 2 | ||||
| -rw-r--r-- | debug/targets/freedom-u500-sim/openocd.cfg | 4 | ||||
| -rw-r--r-- | debug/targets/freedom-u500/openocd.cfg | 2 | ||||
| -rw-r--r-- | debug/testlib.py | 7 |
8 files changed, 29 insertions, 9 deletions
diff --git a/debug/programs/entry.S b/debug/programs/entry.S index e021860..c9e319c 100755 --- a/debug/programs/entry.S +++ b/debug/programs/entry.S @@ -30,8 +30,23 @@ handle_reset: la t0, trap_entry csrw mtvec, t0 csrwi mstatus, 0 + + // make sure these registers exist by seeing if either S or U bits + // are set before attempting to zero them out. + csrr t1, misa + addi t2, x0, 1 + slli t2, t2, 20 // U_EXTENSION + and t2, t1, t2 + bne x0, t2, 1f + addi t2, x0, 1 + slli t2, t2, 18 // S_EXTENSION + and t2, t1, t2 + bne x0, t2, 1f + j 2f +1: csrwi mideleg, 0 csrwi medeleg, 0 +2: csrwi mie, 0 # initialize global pointer diff --git a/debug/programs/mprv.S b/debug/programs/mprv.S index 574f32e..cc1ca54 100644 --- a/debug/programs/mprv.S +++ b/debug/programs/mprv.S @@ -13,9 +13,9 @@ main: # update mstatus csrr t1, CSR_MSTATUS #if XLEN == 32 - li t0, (MSTATUS_MPRV | (VM_SV32 << 24)) + li t0, (MSTATUS_MPRV | (SPTBR_MODE_SV32 << 24)) #else - li t0, (MSTATUS_MPRV | (VM_SV39 << 24)) + li t0, (MSTATUS_MPRV | (SPTBR_MODE_SV39 << 24)) #endif #li t0, ((VM_SV39 << 24)) or t1, t0, t1 diff --git a/debug/targets/HiFive1/openocd.cfg b/debug/targets/HiFive1/openocd.cfg index d2c2879..72a5446 100644 --- a/debug/targets/HiFive1/openocd.cfg +++ b/debug/targets/HiFive1/openocd.cfg @@ -14,7 +14,7 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME riscv -chain-position $_TARGETNAME -$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1 +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1 -rtos riscv flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME init diff --git a/debug/targets/freedom-e300-sim/openocd.cfg b/debug/targets/freedom-e300-sim/openocd.cfg index f3d9cb4..fcb8451 100644 --- a/debug/targets/freedom-e300-sim/openocd.cfg +++ b/debug/targets/freedom-e300-sim/openocd.cfg @@ -2,6 +2,7 @@ adapter_khz 10000 source [find interface/jtag_vpi.cfg] jtag_vpi_set_port $::env(JTAG_VPI_PORT) +#jtag_vpi_set_port 34448 set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 @@ -11,3 +12,4 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv init halt +echo "OK GO NOW" diff --git a/debug/targets/freedom-e300/openocd.cfg b/debug/targets/freedom-e300/openocd.cfg index 0596b15..5824b77 100644 --- a/debug/targets/freedom-e300/openocd.cfg +++ b/debug/targets/freedom-e300/openocd.cfg @@ -6,7 +6,7 @@ set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME +target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv gdb_report_data_abort enable diff --git a/debug/targets/freedom-u500-sim/openocd.cfg b/debug/targets/freedom-u500-sim/openocd.cfg index 9239c83..0ce11d8 100644 --- a/debug/targets/freedom-u500-sim/openocd.cfg +++ b/debug/targets/freedom-u500-sim/openocd.cfg @@ -1,8 +1,8 @@ adapter_khz 10000 source [find interface/jtag_vpi.cfg] -jtag_vpi_set_port $::env(JTAG_VPI_PORT) -#jtag_vpi_set_port 44005 +#jtag_vpi_set_port $::env(JTAG_VPI_PORT) +jtag_vpi_set_port 46401 set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 diff --git a/debug/targets/freedom-u500/openocd.cfg b/debug/targets/freedom-u500/openocd.cfg index d448989..3e3bcad 100644 --- a/debug/targets/freedom-u500/openocd.cfg +++ b/debug/targets/freedom-u500/openocd.cfg @@ -6,7 +6,7 @@ set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME +target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv init diff --git a/debug/testlib.py b/debug/testlib.py index 5a5d6e3..b0a625b 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -19,8 +19,11 @@ def find_file(path): return None def compile(args, xlen=32): # pylint: disable=redefined-builtin - cc = os.path.expandvars("$RISCV/bin/riscv%d-unknown-elf-gcc" % xlen) + cc = os.path.expandvars("$RISCV/bin/riscv64-unknown-elf-gcc") cmd = [cc, "-g"] + if (xlen == 32): + cmd.append("-march=rv32imac") + cmd.append("-mabi=ilp32") for arg in args: found = find_file(arg) if found: @@ -28,7 +31,7 @@ def compile(args, xlen=32): # pylint: disable=redefined-builtin else: cmd.append(arg) process = subprocess.Popen(cmd, stdout=subprocess.PIPE, - stderr=subprocess.PIPE) + stderr=subprocess.PIPE) stdout, stderr = process.communicate() if process.returncode: print |