diff options
| -rw-r--r-- | isa/rv64mi/ma_addr.S | 1 | ||||
| -rw-r--r-- | isa/rv64si/ma_fetch.S | 1 | ||||
| -rw-r--r-- | isa/rv64uc/rvc.S | 3 | ||||
| -rw-r--r-- | isa/rv64ui/jalr.S | 1 |
4 files changed, 5 insertions, 1 deletions
diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S index 2f4d96d..721ac6a 100644 --- a/isa/rv64mi/ma_addr.S +++ b/isa/rv64mi/ma_addr.S @@ -13,6 +13,7 @@ RVTEST_RV64M RVTEST_CODE_BEGIN + .align 2 .option norvc la s0, data diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S index 5943456..cd5a22d 100644 --- a/isa/rv64si/ma_fetch.S +++ b/isa/rv64si/ma_fetch.S @@ -23,6 +23,7 @@ RVTEST_CODE_BEGIN #define stvec_handler mtvec_handler #endif + .align 2 .option norvc # Without RVC, the jalr should trap, and the handler will skip ahead. diff --git a/isa/rv64uc/rvc.S b/isa/rv64uc/rvc.S index b0766a9..3629d1d 100644 --- a/isa/rv64uc/rvc.S +++ b/isa/rv64uc/rvc.S @@ -13,11 +13,12 @@ RVTEST_RV64U RVTEST_CODE_BEGIN + .align 2 .option push .option norvc #define RVC_TEST_CASE(n, r, v, code...) \ - TEST_CASE (n, r, v, .option push; .option rvc; code; .option pop) + TEST_CASE (n, r, v, .option push; .option rvc; code; .align 2; .option pop) // Make sure fetching a 4-byte instruction across a page boundary works. li TESTNUM, 2 diff --git a/isa/rv64ui/jalr.S b/isa/rv64ui/jalr.S index d63bbe2..f27005a 100644 --- a/isa/rv64ui/jalr.S +++ b/isa/rv64ui/jalr.S @@ -43,6 +43,7 @@ target_2: #------------------------------------------------------------- .option push + .align 2 .option norvc TEST_CASE( 7, t0, 4, \ li t0, 1; \ |