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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2014-11-13 03:11:05 -0800 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2014-11-13 03:11:05 -0800 |
| commit | 726a546463d5674205f1e8905cc082c6c807e79b (patch) | |
| tree | 7db1dd5c18dc78194acab82f134eb66a947fea92 /isa | |
| parent | edbd1cfa27faa0b5fe51e4708f4fce102a512b16 (diff) | |
| download | riscv-tests-726a546463d5674205f1e8905cc082c6c807e79b.zip riscv-tests-726a546463d5674205f1e8905cc082c6c807e79b.tar.gz riscv-tests-726a546463d5674205f1e8905cc082c6c807e79b.tar.bz2 | |
make rv32si fault load/store test stronger
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv32si/fa_addr_zscale_8192.S | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/isa/rv32si/fa_addr_zscale_8192.S b/isa/rv32si/fa_addr_zscale_8192.S index 8bb110a..37b6edf 100644 --- a/isa/rv32si/fa_addr_zscale_8192.S +++ b/isa/rv32si/fa_addr_zscale_8192.S @@ -58,7 +58,11 @@ loop: li s0, 0xbad1dea0 beq s1, x0, loop - j pass + li TESTNUM, 10 + li s0, 0x1ffc + lw x0, 0(s0) // if an exception is taken, then would fail because evec is set to evec_store + + j pass // this time it should pass TEST_PASSFAIL |