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| author | Andrew Waterman <andrew@sifive.com> | 2017-05-05 14:11:42 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-05-05 14:11:42 -0700 |
| commit | b831fe7f4723ae745c4c31ca0bc628277dba94ef (patch) | |
| tree | b718f3455d10c6bd7c3fa19d36d62e5605026f46 /isa | |
| parent | af832bf8fd7ed43631e1d1ceb66b10027419a4e6 (diff) | |
| download | riscv-tests-b831fe7f4723ae745c4c31ca0bc628277dba94ef.zip riscv-tests-b831fe7f4723ae745c4c31ca0bc628277dba94ef.tar.gz riscv-tests-b831fe7f4723ae745c4c31ca0bc628277dba94ef.tar.bz2 | |
Regularize control flow in dirty-bit test
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv64si/dirty.S | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/isa/rv64si/dirty.S b/isa/rv64si/dirty.S index 17aa57f..50bdcfb 100644 --- a/isa/rv64si/dirty.S +++ b/isa/rv64si/dirty.S @@ -28,7 +28,7 @@ RVTEST_CODE_BEGIN # Try a faulting store to make sure dirty bit is not set li TESTNUM, 2 li t2, 1 - sw t2, dummy - DRAM_BASE, t1 + sw t2, dummy - DRAM_BASE, a0 # Set SUM=1 so user memory access is permitted li TESTNUM, 3 @@ -40,7 +40,7 @@ RVTEST_CODE_BEGIN bnez t0, die # Try a non-faulting store to make sure dirty bit is set - sw t2, dummy - DRAM_BASE, t1 + sw t2, dummy - DRAM_BASE, a0 # Make sure it succeeded lw t0, dummy - DRAM_BASE @@ -52,9 +52,9 @@ RVTEST_CODE_BEGIN # Make sure D bit is set lw t0, page_table_1 - li t1, PTE_A | PTE_D - and t0, t0, t1 - bne t0, t1, die + li a0, PTE_A | PTE_D + and t0, t0, a0 + bne t0, a0, die RVTEST_PASS @@ -81,12 +81,16 @@ skip: 1: li t1, 3 bne TESTNUM, t1, 1f - # The implementation doesn't appear to set D bits in HW. Skip the test, - # after making sure the D bit is clear. + # The implementation doesn't appear to set D bits in HW. + # Make sure the D bit really is clear. lw t0, page_table_1 and t1, t0, PTE_D bnez t1, die - j pass + # Set the D bit. + or t0, t0, PTE_D + sw t0, page_table_1, t1 + sfence.vma + mret 1: die: |