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| author | Tommy Thorn <tommy-github-email@thorn.ws> | 2018-09-06 11:07:42 -0700 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-09-06 11:07:42 -0700 |
| commit | 901a2694d5384e4ef9af8e4fb0c9a07eb24d0028 (patch) | |
| tree | c64794e309aacec160723df44ec7915469b7ea6d /isa | |
| parent | 79064081503b53fdb44094e32ff54a3ab20a9bf2 (diff) | |
| download | riscv-tests-901a2694d5384e4ef9af8e4fb0c9a07eb24d0028.zip riscv-tests-901a2694d5384e4ef9af8e4fb0c9a07eb24d0028.tar.gz riscv-tests-901a2694d5384e4ef9af8e4fb0c9a07eb24d0028.tar.bz2 | |
breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) (#159)
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv64mi/breakpoint.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S index 647430b..df415a1 100644 --- a/isa/rv64mi/breakpoint.S +++ b/isa/rv64mi/breakpoint.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN la a2, 1f csrw tdata2, a2 - li a0, MCONTROL_M | MCONTROL_EXECUTE + li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_EXECUTE csrw tdata1, a0 # Skip if breakpoint type is unsupported. csrr a1, tdata1 |