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authorAndrew Waterman <waterman@cs.berkeley.edu>2015-07-06 17:07:02 -0700
committerAndrew Waterman <waterman@cs.berkeley.edu>2015-07-06 17:07:02 -0700
commit3b1a075e871d7c14ba9b2983183eb8a4a3916f5e (patch)
treeef9f2e18495c02c84b1f4ea8192fa4d825a50c5b /isa
parent94e0a82bde96bc203bd854efa8ba06c49d16fe75 (diff)
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Coherence torture test for VM tests
VM tests only support one core, so have the other cores hammer on the memory system to attempt to catch simple coherence regressions.
Diffstat (limited to 'isa')
-rw-r--r--isa/Makefile5
1 files changed, 3 insertions, 2 deletions
diff --git a/isa/Makefile b/isa/Makefile
index e4606d5..8f174d1 100644
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -22,8 +22,9 @@ default: all
RISCV_PREFIX=riscv64-unknown-elf-
RISCV_GCC = $(RISCV_PREFIX)gcc
-RISCV_GCC_OPTS = -static -fpic -fvisibility=hidden -nostdlib -nostartfiles -Wa,-march=RVIMAFDXhwacha
-RISCV_OBJDUMP = $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data
+ENTROPY = -DENTROPY=$(shell echo $$$$)
+RISCV_GCC_OPTS = $(ENTROPY) -static -fpic -fvisibility=hidden -nostdlib -nostartfiles -Wa,-march=RVIMAFDXhwacha
+RISCV_OBJDUMP = $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data
RISCV_SIM = spike --extension=hwacha
vpath %.S $(isa_src_dir)