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| author | Andrew Waterman <andrew@sifive.com> | 2016-12-06 17:04:14 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2016-12-06 17:04:14 -0800 |
| commit | 56f46aa0f9688c87ce9ebd7658e19b884b018b6b (patch) | |
| tree | 516d33de0c78bab0968f8548f7223160d8bba6fb /isa/rv64ui | |
| parent | b68b39031a730ecc155ed87fba2ed5f111d0ab07 (diff) | |
| download | riscv-tests-56f46aa0f9688c87ce9ebd7658e19b884b018b6b.zip riscv-tests-56f46aa0f9688c87ce9ebd7658e19b884b018b6b.tar.gz riscv-tests-56f46aa0f9688c87ce9ebd7658e19b884b018b6b.tar.bz2 | |
avoid non-standard predefined macros
Diffstat (limited to 'isa/rv64ui')
| -rw-r--r-- | isa/rv64ui/sll.S | 2 | ||||
| -rw-r--r-- | isa/rv64ui/slli.S | 2 | ||||
| -rw-r--r-- | isa/rv64ui/srl.S | 2 | ||||
| -rw-r--r-- | isa/rv64ui/srli.S | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/isa/rv64ui/sll.S b/isa/rv64ui/sll.S index 31037d1..257aa9d 100644 --- a/isa/rv64ui/sll.S +++ b/isa/rv64ui/sll.S @@ -42,7 +42,7 @@ RVTEST_CODE_BEGIN TEST_RR_OP( 19, sll, 0x0000001090909080, 0x0000000021212121, 0xffffffffffffffc7 ); TEST_RR_OP( 20, sll, 0x0000084848484000, 0x0000000021212121, 0xffffffffffffffce ); -#ifdef __riscv64 +#if __riscv_xlen == 64 TEST_RR_OP( 21, sll, 0x8000000000000000, 0x0000000021212121, 0xffffffffffffffff ); TEST_RR_OP( 50, sll, 0x8000000000000000, 0x0000000000000001, 63 ); TEST_RR_OP( 51, sll, 0xffffff8000000000, 0xffffffffffffffff, 39 ); diff --git a/isa/rv64ui/slli.S b/isa/rv64ui/slli.S index dd02d49..f28ea1c 100644 --- a/isa/rv64ui/slli.S +++ b/isa/rv64ui/slli.S @@ -35,7 +35,7 @@ RVTEST_CODE_BEGIN TEST_IMM_OP( 15, slli, 0x0000084848484000, 0x0000000021212121, 14 ); TEST_IMM_OP( 16, slli, 0x1090909080000000, 0x0000000021212121, 31 ); -#ifdef __riscv64 +#if __riscv_xlen == 64 TEST_RR_OP( 50, sll, 0x8000000000000000, 0x0000000000000001, 63 ); TEST_RR_OP( 51, sll, 0xffffff8000000000, 0xffffffffffffffff, 39 ); TEST_RR_OP( 52, sll, 0x0909080000000000, 0x0000000021212121, 43 ); diff --git a/isa/rv64ui/srl.S b/isa/rv64ui/srl.S index ad5c2e5..c1e936a 100644 --- a/isa/rv64ui/srl.S +++ b/isa/rv64ui/srl.S @@ -18,7 +18,7 @@ RVTEST_CODE_BEGIN #------------------------------------------------------------- #define TEST_SRL(n, v, a) \ - TEST_RR_OP(n, srl, ((v) & ((1 << (_RISCV_SZLONG-1) << 1) - 1)) >> (a), v, a) + TEST_RR_OP(n, srl, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a) TEST_SRL( 2, 0xffffffff80000000, 0 ); TEST_SRL( 3, 0xffffffff80000000, 1 ); diff --git a/isa/rv64ui/srli.S b/isa/rv64ui/srli.S index eae2532..88ee8d2 100644 --- a/isa/rv64ui/srli.S +++ b/isa/rv64ui/srli.S @@ -18,7 +18,7 @@ RVTEST_CODE_BEGIN #------------------------------------------------------------- #define TEST_SRL(n, v, a) \ - TEST_IMM_OP(n, srli, ((v) & ((1 << (_RISCV_SZLONG-1) << 1) - 1)) >> (a), v, a) + TEST_IMM_OP(n, srli, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a) TEST_SRL( 2, 0xffffffff80000000, 0 ); TEST_SRL( 3, 0xffffffff80000000, 1 ); |