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author | Palmer Dabbelt <palmer@dabbelt.com> | 2016-07-12 09:19:08 -0700 |
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committer | Palmer Dabbelt <palmer@dabbelt.com> | 2016-07-12 09:19:08 -0700 |
commit | 00df2be7a414d34c7633142c73ac6130f6cbbd4b (patch) | |
tree | 49ade5408f077f851fd90280fc300709148883f9 /isa/rv32um/rem.S | |
parent | d82a880f81cb5d197f712bbd17e821e0d70d7b75 (diff) | |
parent | 3dc00e7b04834f862a074ac8822892e1ecfc009c (diff) | |
download | riscv-tests-00df2be7a414d34c7633142c73ac6130f6cbbd4b.zip riscv-tests-00df2be7a414d34c7633142c73ac6130f6cbbd4b.tar.gz riscv-tests-00df2be7a414d34c7633142c73ac6130f6cbbd4b.tar.bz2 |
Merge commit '3dc00e7' into smi-demosmi-demo
Diffstat (limited to 'isa/rv32um/rem.S')
-rw-r--r-- | isa/rv32um/rem.S | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/isa/rv32um/rem.S b/isa/rv32um/rem.S new file mode 100644 index 0000000..c318e2c --- /dev/null +++ b/isa/rv32um/rem.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rem.S +#----------------------------------------------------------------------------- +# +# Test rem instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rem, 2, 20, 6 ); + TEST_RR_OP( 3, rem, -2, -20, 6 ); + TEST_RR_OP( 4, rem, 2, 20, -6 ); + TEST_RR_OP( 5, rem, -2, -20, -6 ); + + TEST_RR_OP( 6, rem, 0, -1<<63, 1 ); + TEST_RR_OP( 7, rem, 0, -1<<63, -1 ); + + TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 ); + TEST_RR_OP( 9, rem, 1, 1, 0 ); + TEST_RR_OP(10, rem, 0, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END |