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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-03-12 17:39:44 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-03-12 17:39:44 -0700 |
| commit | 7864b6441aad0bca337eb70fcd12394cc68bddc6 (patch) | |
| tree | 04e9cc542d46b016706e1761100db94c2fc75b9c /isa/rv32ui | |
| parent | d7dba3cbb448b2deeefa54653c7fcaab7e22940f (diff) | |
| download | riscv-tests-7864b6441aad0bca337eb70fcd12394cc68bddc6.zip riscv-tests-7864b6441aad0bca337eb70fcd12394cc68bddc6.tar.gz riscv-tests-7864b6441aad0bca337eb70fcd12394cc68bddc6.tar.bz2 | |
Update to new privileged spec
Diffstat (limited to 'isa/rv32ui')
| -rw-r--r-- | isa/rv32ui/lrsc.S | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/isa/rv32ui/lrsc.S b/isa/rv32ui/lrsc.S index f559f29..2aee818 100644 --- a/isa/rv32ui/lrsc.S +++ b/isa/rv32ui/lrsc.S @@ -13,13 +13,17 @@ RVTEST_RV32U RVTEST_CODE_BEGIN -# wait for all cores to boot +# get a unique core id la a0, coreid li a1, 1 amoadd.w a2, a1, (a0) -lw a3, 4(x0) + +# for now, only run this on core 0 +1:li a3, 1 +bgeu a2, a3, 1b + 1: lw a1, (a0) -blt a1, a3, 1b +bltu a1, a3, 1b # make sure that sc without a reservation fails. TEST_CASE( 2, a4, 1, \ |