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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-02-19 12:25:14 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-02-19 12:25:39 -0800 |
| commit | e0532426bcd8634041be23457ff78a90e78db466 (patch) | |
| tree | 9b6c74f81bd7f3c3f36a361253567c394d31c7b1 /isa/rv32si | |
| parent | d7aa5a3443f7a91d108be67f91900261e94d0ccd (diff) | |
| download | riscv-tests-e0532426bcd8634041be23457ff78a90e78db466.zip riscv-tests-e0532426bcd8634041be23457ff78a90e78db466.tar.gz riscv-tests-e0532426bcd8634041be23457ff78a90e78db466.tar.bz2 | |
Unify rv32/rv64 timer tests
Diffstat (limited to 'isa/rv32si')
| -rw-r--r-- | isa/rv32si/timer.S | 41 |
1 files changed, 3 insertions, 38 deletions
diff --git a/isa/rv32si/timer.S b/isa/rv32si/timer.S index 0e3a623..5c627d5 100644 --- a/isa/rv32si/timer.S +++ b/isa/rv32si/timer.S @@ -10,42 +10,7 @@ #include "riscv_test.h" #include "test_macros.h" -RVTEST_RV32S -RVTEST_CODE_BEGIN +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32S - la t0, evec - csrw evec, t0 - - csrr t0, count - add t0, t0, 1000 - csrw compare, t0 - - li t1, 1<<23 - csrs status, t1 # turn on timer IRQ 7 - csrsi status, 4 # enable interrupts - - li TESTNUM, 2 - li a0,10000 -loop: - div x0, x0, x0 - addi a0, a0, -1 - bne a0, x0, loop - j fail # assumption is that you can't divide in one cycle - - TEST_PASSFAIL - -evec: - li TESTNUM, 3 - li t1, 0x80000000|IRQ_TIMER - csrr t0, cause - bne t0, t1, fail - j pass - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END +#include "../rv64si/timer.S" |