Update to new privileged spec

8 files changed, 43 insertions, 84 deletions

diff --git a/isa/rv32si/Makefrag b/isa/rv32si/Makefrag
index 024a9a0..70cea70 100644
--- a/isa/rv32si/Makefrag
+++ b/isa/rv32si/Makefrag
@@ -7,7 +7,6 @@ rv32si_sc_tests = \
 	shamt \
 	ma_fetch \
 	illegal \
-	privileged \
 	scall \
 	sbreak \
 	ma_addr \
diff --git a/isa/rv32si/illegal.S b/isa/rv32si/illegal.S
index aa97932..3bec030 100644
--- a/isa/rv32si/illegal.S
+++ b/isa/rv32si/illegal.S
@@ -13,8 +13,8 @@
 RVTEST_RV32S
 RVTEST_CODE_BEGIN
 
-  la t0, evec
-  csrw evec, t0
+  la t0, stvec
+  csrw stvec, t0
 
   li TESTNUM, 2
   .word 0
@@ -24,13 +24,13 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-evec:
+stvec:
   li t1, CAUSE_ILLEGAL_INSTRUCTION
-  csrr t0, cause
+  csrr t0, scause
   bne t0, t1, fail
-  csrr t0, epc
+  csrr t0, sepc
   addi t0, t0, 8
-  csrw epc, t0
+  csrw sepc, t0
   sret
 
 RVTEST_CODE_END
diff --git a/isa/rv32si/ma_addr.S b/isa/rv32si/ma_addr.S
index 897282e..13ac778 100644
--- a/isa/rv32si/ma_addr.S
+++ b/isa/rv32si/ma_addr.S
@@ -13,10 +13,10 @@
 RVTEST_RV32S
 RVTEST_CODE_BEGIN
 
-  la s0, evec_load
+  la s0, stvec_load
 
-  la t0, evec_load
-  csrw evec, t0
+  la t0, stvec_load
+  csrw stvec, t0
 
   li TESTNUM, 2
   lw x0, 1(s0)
@@ -38,8 +38,8 @@ RVTEST_CODE_BEGIN
   lhu x0, 1(s0)
   j fail
 
-  la t0, evec_store
-  csrw evec, t0
+  la t0, stvec_store
+  csrw stvec, t0
 
   li TESTNUM, 7
   sw x0, 1(s0)
@@ -61,22 +61,22 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-evec_load:
+stvec_load:
   li t1, CAUSE_MISALIGNED_LOAD
-  csrr t0, cause
+  csrr t0, scause
   bne t0, t1, fail
-  csrr t0, epc
+  csrr t0, sepc
   addi t0, t0, 8
-  csrw epc, t0
+  csrw sepc, t0
   sret
 
-evec_store:
+stvec_store:
   li t1, CAUSE_MISALIGNED_STORE
-  csrr t0, cause
+  csrr t0, scause
   bne t0, t1, fail
-  csrr t0, epc
+  csrr t0, sepc
   addi t0, t0, 8
-  csrw epc, t0
+  csrw sepc, t0
   sret
 
 RVTEST_CODE_END
diff --git a/isa/rv32si/ma_fetch.S b/isa/rv32si/ma_fetch.S
index f310630..4aa7973 100644
--- a/isa/rv32si/ma_fetch.S
+++ b/isa/rv32si/ma_fetch.S
@@ -13,8 +13,8 @@
 RVTEST_RV32S
 RVTEST_CODE_BEGIN
 
-  la t0, evec
-  csrw evec, t0
+  la t0, stvec
+  csrw stvec, t0
 
   li TESTNUM, 2
   la t0, 1f
@@ -38,17 +38,17 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-evec:
+stvec:
   li t0, 3
   beq TESTNUM, t0, fail
 
   li t1, CAUSE_MISALIGNED_FETCH
-  csrr t0, cause
+  csrr t0, scause
   bne t0, t1, fail
   li t1, 0
-  csrr t0, epc
+  csrr t0, sepc
   addi t0, t0, 2 // skip over instruction after jalr
-  csrw epc, t0
+  csrw sepc, t0
   sret
 
 RVTEST_CODE_END
diff --git a/isa/rv32si/privileged.S b/isa/rv32si/privileged.S
deleted file mode 100644
index 519de80..0000000
--- a/isa/rv32si/privileged.S
+++ /dev/null
@@ -1,40 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# privileged.S
-#-----------------------------------------------------------------------------
-#
-# Test privileged instruction trap.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32S
-RVTEST_CODE_BEGIN
-
-  la t0, evec
-  csrw evec, t0
-
-  csrci status, 1
-
-  li TESTNUM, 2
-  sret
-  j fail
-
-  TEST_PASSFAIL
-
-evec:
-  li t1, CAUSE_PRIVILEGED_INSTRUCTION
-  csrr t0, cause
-  bne t0, t1, fail
-  j pass
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END
diff --git a/isa/rv32si/sbreak.S b/isa/rv32si/sbreak.S
index 4349b35..cd920db 100644
--- a/isa/rv32si/sbreak.S
+++ b/isa/rv32si/sbreak.S
@@ -13,8 +13,8 @@
 RVTEST_RV32S
 RVTEST_CODE_BEGIN
 
-  la t0, evec
-  csrw evec, t0
+  la t0, stvec
+  csrw stvec, t0
 
   li TESTNUM, 2
   sbreak
@@ -24,13 +24,13 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-evec:
+stvec:
   li t1, CAUSE_BREAKPOINT
-  csrr t0, cause
+  csrr t0, scause
   bne t0, t1, fail
-  csrr t0, epc
+  csrr t0, sepc
   addi t0, t0, 8
-  csrw epc, t0
+  csrw sepc, t0
   sret
 
 RVTEST_CODE_END
diff --git a/isa/rv32si/scall.S b/isa/rv32si/scall.S
index 3dda8b1..c5cc3ac 100644
--- a/isa/rv32si/scall.S
+++ b/isa/rv32si/scall.S
@@ -13,8 +13,8 @@
 RVTEST_RV32S
 RVTEST_CODE_BEGIN
 
-  la t0, evec
-  csrw evec, t0
+  la t0, stvec
+  csrw stvec, t0
 
   li TESTNUM, 2
   scall
@@ -24,13 +24,13 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-evec:
-  li t1, CAUSE_SYSCALL
-  csrr t0, cause
+stvec:
+  li t1, CAUSE_SCALL
+  csrr t0, scause
   bne t0, t1, fail
-  csrr t0, epc
+  csrr t0, sepc
   addi t0, t0, 8
-  csrw epc, t0
+  csrw sepc, t0
   sret
 
 RVTEST_CODE_END
diff --git a/isa/rv32si/shamt.S b/isa/rv32si/shamt.S
index ee1c8b5..4fe7c2f 100644
--- a/isa/rv32si/shamt.S
+++ b/isa/rv32si/shamt.S
@@ -13,25 +13,25 @@
 RVTEST_RV32S
 RVTEST_CODE_BEGIN
 
-  la t0, evec
-  csrw evec, t0
+  la t0, stvec
+  csrw stvec, t0
 
   # Make sure slli with shamt[4] set is legal.
   TEST_CASE( 2, a0, 65536, li a0, 1; slli a0, a0, 16);
 
-  # Make sure slli with shamt[4] set is not legal.
+  # Make sure slli with shamt[5] set is not legal.
   TEST_CASE( 3, x0, 1, slli a0, a0, 32);
 
   TEST_PASSFAIL
 
-evec:
+stvec:
   # Trapping on test 3 is good.
   # Note that since the test didn't complete, TESTNUM is smaller by 1.
   li t0, 2
   bne TESTNUM, t0, fail
 
   # Make sure CAUSE indicates an illegal instructino.
-  csrr t0, cause
+  csrr t0, scause
   li t1, CAUSE_ILLEGAL_INSTRUCTION
   bne t0, t1, fail
   j pass