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authorTim Newsome <tim@sifive.com>2016-10-03 10:40:17 -0700
committerTim Newsome <tim@sifive.com>2016-10-03 10:40:17 -0700
commitacb593160f2f7e22bfd6a480570f2c5094634165 (patch)
tree7216a74ac15231f8b3245268bd57da76bdae0208 /debug
parentead84fbc720db4c8f42bb6a7ae979dbb4f8f6c5d (diff)
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Add test for memory read from invalid address.
Diffstat (limited to 'debug')
-rwxr-xr-xdebug/gdbserver.py10
-rw-r--r--debug/targets/freedom-e300/openocd.cfg2
2 files changed, 12 insertions, 0 deletions
diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index 81aafa3..91c385f 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -293,6 +293,16 @@ class MemTest64(SimpleMemoryTest):
def test(self):
self.access_test(8, 'long long')
+class MemTestReadInvalid(SimpleMemoryTest):
+ def test(self):
+ # This test relies on 'gdb_report_data_abort enable' being executed in
+ # the openocd.cfg file.
+ try:
+ self.gdb.p("*((int*)0xdeadbeef)")
+ assert False, "Access should have failed."
+ except testlib.CannotAccess as e:
+ assertEqual(e.address, 0xdeadbeef)
+
class MemTestBlock(GdbTest):
def test(self):
length = 1024
diff --git a/debug/targets/freedom-e300/openocd.cfg b/debug/targets/freedom-e300/openocd.cfg
index d448989..0596b15 100644
--- a/debug/targets/freedom-e300/openocd.cfg
+++ b/debug/targets/freedom-e300/openocd.cfg
@@ -8,6 +8,8 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+gdb_report_data_abort enable
+
init
halt