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| author | Richard Xia <rxia@sifive.com> | 2017-05-23 13:38:08 -0700 |
|---|---|---|
| committer | Richard Xia <rxia@sifive.com> | 2017-05-23 13:38:08 -0700 |
| commit | 3cd7f374258f7c4ddaa4e0d835a149f185308d28 (patch) | |
| tree | 78da989bceb95636698b3deb79e7103b5cdb1678 /debug/testlib.py | |
| parent | 5ff7b723976b3736daa0f0ad5df71d40576a674a (diff) | |
| download | riscv-tests-3cd7f374258f7c4ddaa4e0d835a149f185308d28.zip riscv-tests-3cd7f374258f7c4ddaa4e0d835a149f185308d28.tar.gz riscv-tests-3cd7f374258f7c4ddaa4e0d835a149f185308d28.tar.bz2 | |
Fail if simulator exits early.
Diffstat (limited to 'debug/testlib.py')
| -rw-r--r-- | debug/testlib.py | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/debug/testlib.py b/debug/testlib.py index b5bd992..3d08e9b 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -132,6 +132,12 @@ class VcsSim(object): stdout=logfile, stderr=logfile) done = False while not done: + # Fail if VCS exits early + exit_code = self.process.poll() + if exit_code is not None: + raise RuntimeError('VCS simulator exited early with status %d' + % exit_code) + line = listenfile.readline() if not line: time.sleep(1) |