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| author | Megan Wachs <megan@sifive.com> | 2017-04-17 11:34:33 -0700 |
|---|---|---|
| committer | Megan Wachs <megan@sifive.com> | 2017-04-17 11:34:33 -0700 |
| commit | eca66b135bbbc4fb804ac49a93fb2bf70f6e739f (patch) | |
| tree | 9e5b8001bccf0a85a1792ab3479734aadc5f0e57 /debug/targets | |
| parent | d76b30df333659baf81b8411c7144378b735062a (diff) | |
| parent | 3429eb68637ff9e25d678d7e2b5f636ab409543c (diff) | |
| download | riscv-tests-eca66b135bbbc4fb804ac49a93fb2bf70f6e739f.zip riscv-tests-eca66b135bbbc4fb804ac49a93fb2bf70f6e739f.tar.gz riscv-tests-eca66b135bbbc4fb804ac49a93fb2bf70f6e739f.tar.bz2 | |
Merge remote-tracking branch 'origin/newprogram' into debug-0.13
Diffstat (limited to 'debug/targets')
| -rw-r--r-- | debug/targets/HiFive1/openocd.cfg | 2 | ||||
| -rw-r--r-- | debug/targets/freedom-e300-sim/openocd.cfg | 5 | ||||
| -rw-r--r-- | debug/targets/freedom-e300/openocd.cfg | 2 | ||||
| -rw-r--r-- | debug/targets/freedom-u500-sim/openocd.cfg | 6 | ||||
| -rw-r--r-- | debug/targets/freedom-u500/openocd.cfg | 2 |
5 files changed, 10 insertions, 7 deletions
diff --git a/debug/targets/HiFive1/openocd.cfg b/debug/targets/HiFive1/openocd.cfg index d2c2879..72a5446 100644 --- a/debug/targets/HiFive1/openocd.cfg +++ b/debug/targets/HiFive1/openocd.cfg @@ -14,7 +14,7 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME riscv -chain-position $_TARGETNAME -$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1 +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1 -rtos riscv flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME init diff --git a/debug/targets/freedom-e300-sim/openocd.cfg b/debug/targets/freedom-e300-sim/openocd.cfg index 0b80885..fcb8451 100644 --- a/debug/targets/freedom-e300-sim/openocd.cfg +++ b/debug/targets/freedom-e300-sim/openocd.cfg @@ -2,13 +2,14 @@ adapter_khz 10000 source [find interface/jtag_vpi.cfg] jtag_vpi_set_port $::env(JTAG_VPI_PORT) +#jtag_vpi_set_port 34448 set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME +target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv init - halt +echo "OK GO NOW" diff --git a/debug/targets/freedom-e300/openocd.cfg b/debug/targets/freedom-e300/openocd.cfg index 0596b15..5824b77 100644 --- a/debug/targets/freedom-e300/openocd.cfg +++ b/debug/targets/freedom-e300/openocd.cfg @@ -6,7 +6,7 @@ set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME +target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv gdb_report_data_abort enable diff --git a/debug/targets/freedom-u500-sim/openocd.cfg b/debug/targets/freedom-u500-sim/openocd.cfg index 0b80885..0ce11d8 100644 --- a/debug/targets/freedom-u500-sim/openocd.cfg +++ b/debug/targets/freedom-u500-sim/openocd.cfg @@ -1,14 +1,16 @@ adapter_khz 10000 source [find interface/jtag_vpi.cfg] -jtag_vpi_set_port $::env(JTAG_VPI_PORT) +#jtag_vpi_set_port $::env(JTAG_VPI_PORT) +jtag_vpi_set_port 46401 set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME +target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv init halt +echo "OK GO NOW" diff --git a/debug/targets/freedom-u500/openocd.cfg b/debug/targets/freedom-u500/openocd.cfg index d448989..3e3bcad 100644 --- a/debug/targets/freedom-u500/openocd.cfg +++ b/debug/targets/freedom-u500/openocd.cfg @@ -6,7 +6,7 @@ set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME +target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv init |