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| author | Tim Newsome <tim@sifive.com> | 2019-05-16 14:39:28 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-16 14:39:28 -0700 |
| commit | b7a0a80210c77c1d817243963ce35fba3ec97851 (patch) | |
| tree | baa8d87e2f8ef6c62948b061856fcaf7347515d1 /debug/targets | |
| parent | fbf5f3a2589c61d34569524dbf353beda0b6b4de (diff) | |
| download | riscv-tests-b7a0a80210c77c1d817243963ce35fba3ec97851.zip riscv-tests-b7a0a80210c77c1d817243963ce35fba3ec97851.tar.gz riscv-tests-b7a0a80210c77c1d817243963ce35fba3ec97851.tar.bz2 | |
Cover with/without halt groups. (#191)
Also work with the new command line options that were renamed in
https://github.com/riscv/riscv-isa-sim/pull/299
Diffstat (limited to 'debug/targets')
| -rw-r--r-- | debug/targets/RISC-V/spike32-2-hwthread.py | 4 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike32-2-rtos.py | 3 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike32-2.py | 2 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike32.py | 2 |
4 files changed, 6 insertions, 5 deletions
diff --git a/debug/targets/RISC-V/spike32-2-hwthread.py b/debug/targets/RISC-V/spike32-2-hwthread.py index 333a7f2..c5fe92d 100644 --- a/debug/targets/RISC-V/spike32-2-hwthread.py +++ b/debug/targets/RISC-V/spike32-2-hwthread.py @@ -8,7 +8,7 @@ class spike32_2(targets.Target): openocd_config_path = "spike-2-hwthread.cfg" timeout_sec = 5 implements_custom_test = True - support_hasel = False def create(self): - return testlib.Spike(self, support_hasel=False) + return testlib.Spike(self, support_hasel=True, + support_haltgroups=False) diff --git a/debug/targets/RISC-V/spike32-2-rtos.py b/debug/targets/RISC-V/spike32-2-rtos.py index 3a2e8b8..335a3d7 100644 --- a/debug/targets/RISC-V/spike32-2-rtos.py +++ b/debug/targets/RISC-V/spike32-2-rtos.py @@ -12,4 +12,5 @@ class spike32_2(targets.Target): def create(self): return testlib.Spike(self, progbufsize=0, dmi_rti=4, - support_hasel=False, support_abstract_csr=True) + support_hasel=False, support_abstract_csr=True, + support_haltgroups=False) diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py index a6fac39..6203214 100644 --- a/debug/targets/RISC-V/spike32-2.py +++ b/debug/targets/RISC-V/spike32-2.py @@ -11,4 +11,4 @@ class spike32_2(targets.Target): def create(self): return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0, dmi_rti=4, - support_abstract_csr=True) + support_abstract_csr=True, support_haltgroups=False) diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py index 6894bcf..e8726b9 100644 --- a/debug/targets/RISC-V/spike32.py +++ b/debug/targets/RISC-V/spike32.py @@ -18,4 +18,4 @@ class spike32(targets.Target): def create(self): # 64-bit FPRs on 32-bit target return testlib.Spike(self, isa="RV32IMAFDC", dmi_rti=4, - support_abstract_csr=True) + support_abstract_csr=True, support_haltgroups=False) |