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| author | Tim Newsome <tim@sifive.com> | 2016-06-10 10:45:27 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-07-18 18:51:54 -0700 |
| commit | 6ccc0bdde5eea898e88961f49e755bd2b4577792 (patch) | |
| tree | 20320df9cab3b239c310f589b6c38364c32f1df3 /debug/targets | |
| parent | 2088d1bce6558a101c42861dc578f4c7d7f4f6b4 (diff) | |
| download | riscv-tests-6ccc0bdde5eea898e88961f49e755bd2b4577792.zip riscv-tests-6ccc0bdde5eea898e88961f49e755bd2b4577792.tar.gz riscv-tests-6ccc0bdde5eea898e88961f49e755bd2b4577792.tar.bz2 | |
Add simple register tests.
Make the RegsTest case a bit more comprehensible.
Diffstat (limited to 'debug/targets')
| -rw-r--r-- | debug/targets/m2gl_m2s/openocd.cfg | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/debug/targets/m2gl_m2s/openocd.cfg b/debug/targets/m2gl_m2s/openocd.cfg index 0e1a491..da20ccc 100644 --- a/debug/targets/m2gl_m2s/openocd.cfg +++ b/debug/targets/m2gl_m2s/openocd.cfg @@ -16,4 +16,4 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME init #reset -#halt +halt |