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authorTim Newsome <tim@sifive.com>2017-09-21 15:19:47 -0700
committerTim Newsome <tim@sifive.com>2017-09-21 15:19:47 -0700
commit35c41f1391b51d4d9c4e0ab40fdfc45dbea346b2 (patch)
treeea793ff318c16acb13a1b21063fd9544786bbba6 /debug/targets
parentfcd0e956339560021e2a16a143697b8123f227d6 (diff)
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Add coverage for single-core non-rtos OpenOCD.
Diffstat (limited to 'debug/targets')
-rw-r--r--debug/targets/RISC-V/spike-rtos.cfg16
-rw-r--r--debug/targets/RISC-V/spike.cfg2
-rw-r--r--debug/targets/RISC-V/spike32-2.py2
-rw-r--r--debug/targets/RISC-V/spike64-2.py2
4 files changed, 19 insertions, 3 deletions
diff --git a/debug/targets/RISC-V/spike-rtos.cfg b/debug/targets/RISC-V/spike-rtos.cfg
new file mode 100644
index 0000000..9b1841c
--- /dev/null
+++ b/debug/targets/RISC-V/spike-rtos.cfg
@@ -0,0 +1,16 @@
+adapter_khz 10000
+
+interface remote_bitbang
+remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
+remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
+
+gdb_report_data_abort enable
+
+init
+reset halt
diff --git a/debug/targets/RISC-V/spike.cfg b/debug/targets/RISC-V/spike.cfg
index 9b1841c..fc20b53 100644
--- a/debug/targets/RISC-V/spike.cfg
+++ b/debug/targets/RISC-V/spike.cfg
@@ -8,7 +8,7 @@ set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
gdb_report_data_abort enable
diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py
index 6cf558d..a7b9a1c 100644
--- a/debug/targets/RISC-V/spike32-2.py
+++ b/debug/targets/RISC-V/spike32-2.py
@@ -5,7 +5,7 @@ import spike32 # pylint: disable=import-error
class spike32_2(targets.Target):
harts = [spike32.spike32_hart(), spike32.spike32_hart()]
- openocd_config_path = "spike.cfg"
+ openocd_config_path = "spike-rtos.cfg"
timeout_sec = 30
def create(self):
diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py
index c6321dc..4f6f1ff 100644
--- a/debug/targets/RISC-V/spike64-2.py
+++ b/debug/targets/RISC-V/spike64-2.py
@@ -5,7 +5,7 @@ import spike64 # pylint: disable=import-error
class spike64_2(targets.Target):
harts = [spike64.spike64_hart(), spike64.spike64_hart()]
- openocd_config_path = "spike.cfg"
+ openocd_config_path = "spike-rtos.cfg"
timeout_sec = 30
def create(self):