Move target definition into individual files.

Instead of defining each target in targets.py, now each target gets its
own .py file. This means people can easily keep their own target files
around that they may not want to put into the main test source. As part
of that, I removed the freedom-u500-sim target since I assume it's only
used internally at SiFive.

Added a few cleanups as well:
* Update README examples, mostly --sim_cmd instead of --cmd.
* Allow defining misa in a target, to skip running of ExamineTarget.
* Rename target.target() to target.create(), which is less confusing.
* Default --sim_cmd to `spike`
* Got rid of `use_fpu`, instead looking at F or D in $misa.

21 files changed, 74 insertions, 148 deletions

diff --git a/debug/targets/spike32/openocd.cfg b/debug/targets/RISC-V/spike32.cfg
index 2742335..2742335 100644
--- a/debug/targets/spike32/openocd.cfg
+++ b/debug/targets/RISC-V/spike32.cfg
diff --git a/debug/targets/spike32/link.lds b/debug/targets/RISC-V/spike32.lds
index 01d0e3d..01d0e3d 100755
--- a/debug/targets/spike32/link.lds
+++ b/debug/targets/RISC-V/spike32.lds
diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py
new file mode 100644
index 0000000..3bf8b47
--- /dev/null
+++ b/debug/targets/RISC-V/spike32.py
@@ -0,0 +1,12 @@
+import targets
+import testlib
+
+class spike32(targets.Target):
+    xlen = 32
+    ram = 0x10000000
+    ram_size = 0x10000000
+    instruction_hardware_breakpoint_count = 4
+    reset_vector = 0x1000
+
+    def create(self):
+        return testlib.Spike(self)
diff --git a/debug/targets/spike64/openocd.cfg b/debug/targets/RISC-V/spike64.cfg
index 2742335..2742335 100644
--- a/debug/targets/spike64/openocd.cfg
+++ b/debug/targets/RISC-V/spike64.cfg
diff --git a/debug/targets/spike64/link.lds b/debug/targets/RISC-V/spike64.lds
index dc7cb63..dc7cb63 100755
--- a/debug/targets/spike64/link.lds
+++ b/debug/targets/RISC-V/spike64.lds
diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py
new file mode 100644
index 0000000..c705857
--- /dev/null
+++ b/debug/targets/RISC-V/spike64.py
@@ -0,0 +1,12 @@
+import targets
+import testlib
+
+class spike64(targets.Target):
+    xlen = 64
+    ram = 0x1212340000
+    ram_size = 0x10000000
+    instruction_hardware_breakpoint_count = 4
+    reset_vector = 0x1000
+
+    def create(self):
+        return testlib.Spike(self)
diff --git a/debug/targets/SiFive/Freedom/E300.py b/debug/targets/SiFive/Freedom/E300.py
new file mode 100644
index 0000000..95ddcfd
--- /dev/null
+++ b/debug/targets/SiFive/Freedom/E300.py
@@ -0,0 +1,9 @@
+import targets
+
+class E300(targets.Target):
+    xlen = 32
+    ram = 0x80000000
+    ram_size = 16 * 1024
+    instruction_hardware_breakpoint_count = 2
+    openocd_config_path = "Freedom.cfg"
+    link_script_path = "Freedom.lds"
diff --git a/debug/targets/SiFive/Freedom/E300Sim.py b/debug/targets/SiFive/Freedom/E300Sim.py
new file mode 100644
index 0000000..e98c5b9
--- /dev/null
+++ b/debug/targets/SiFive/Freedom/E300Sim.py
@@ -0,0 +1,13 @@
+import targets
+
+class E300Sim(targets.Target):
+    xlen = 32
+    timeout_sec = 6000
+    ram = 0x80000000
+    ram_size = 256 * 1024 * 1024
+    instruction_hardware_breakpoint_count = 2
+    openocd_config_path = "Freedom.cfg"
+    link_script_path = "Freedom.lds"
+
+    def target(self):
+        return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
diff --git a/debug/targets/freedom-u500/openocd.cfg b/debug/targets/SiFive/Freedom/Freedom.cfg
index 8947bf5..8947bf5 100644
--- a/debug/targets/freedom-u500/openocd.cfg
+++ b/debug/targets/SiFive/Freedom/Freedom.cfg
diff --git a/debug/targets/HiFive1/link.lds b/debug/targets/SiFive/Freedom/Freedom.lds
index 1e0645a..1e0645a 100755..100644
--- a/debug/targets/HiFive1/link.lds
+++ b/debug/targets/SiFive/Freedom/Freedom.lds
diff --git a/debug/targets/SiFive/Freedom/U500.py b/debug/targets/SiFive/Freedom/U500.py
new file mode 100644
index 0000000..c22aa4c
--- /dev/null
+++ b/debug/targets/SiFive/Freedom/U500.py
@@ -0,0 +1,9 @@
+import targets
+
+class U500(targets.Target):
+    xlen = 64
+    ram = 0x80000000
+    ram_size = 16 * 1024
+    instruction_hardware_breakpoint_count = 2
+    openocd_config_path = "Freedom.cfg"
+    link_script_path = "Freedom.lds"
diff --git a/debug/targets/SiFive/Freedom/U500Sim.py b/debug/targets/SiFive/Freedom/U500Sim.py
new file mode 100644
index 0000000..7648960
--- /dev/null
+++ b/debug/targets/SiFive/Freedom/U500Sim.py
@@ -0,0 +1,11 @@
+class U500Sim(Target):
+    xlen = 64
+    timeout_sec = 6000
+    ram = 0x80000000
+    ram_size = 256 * 1024 * 1024
+    instruction_hardware_breakpoint_count = 2
+    openocd_config_path = "Freedom.cfg"
+    link_script_path = "Freedom.lds"
+
+    def target(self):
+        return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
diff --git a/debug/targets/HiFive1/openocd.cfg b/debug/targets/SiFive/HiFive1.cfg
index 5bde59b..5bde59b 100644
--- a/debug/targets/HiFive1/openocd.cfg
+++ b/debug/targets/SiFive/HiFive1.cfg
diff --git a/debug/targets/freedom-e300-sim/link.lds b/debug/targets/SiFive/HiFive1.lds
index 1e0645a..1e0645a 100755
--- a/debug/targets/freedom-e300-sim/link.lds
+++ b/debug/targets/SiFive/HiFive1.lds
diff --git a/debug/targets/SiFive/HiFive1.py b/debug/targets/SiFive/HiFive1.py
new file mode 100644
index 0000000..813829e
--- /dev/null
+++ b/debug/targets/SiFive/HiFive1.py
@@ -0,0 +1,8 @@
+import targets
+
+class HiFive1(targets.Target):
+    xlen = 32
+    ram = 0x80000000
+    ram_size = 16 * 1024
+    instruction_hardware_breakpoint_count = 2
+    misa = 0x40001105
diff --git a/debug/targets/freedom-e300-sim/openocd.cfg b/debug/targets/freedom-e300-sim/openocd.cfg
deleted file mode 100644
index 5733f27..0000000
--- a/debug/targets/freedom-e300-sim/openocd.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-adapter_khz     10000
-
-source [find interface/jtag_vpi.cfg]
-jtag_vpi_set_port $::env(JTAG_VPI_PORT)
-#jtag_vpi_set_port 34448
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
-
-init
-halt
-echo "Ready for Remote Connections"
diff --git a/debug/targets/freedom-e300/link.lds b/debug/targets/freedom-e300/link.lds
deleted file mode 100755
index 1e0645a..0000000
--- a/debug/targets/freedom-e300/link.lds
+++ /dev/null
@@ -1,34 +0,0 @@
-OUTPUT_ARCH( "riscv" )
-
-SECTIONS
-{
-  . = 0x80000000;
-  .text : 
-  {
-    *(.text.entry)
-    *(.text)
-  }
-
-  /* data segment */
-  .data : { *(.data) }
-
-  .sdata : {
-    __global_pointer$ = . + 0x800;
-    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
-    *(.srodata*)
-    *(.sdata .sdata.* .gnu.linkonce.s.*)
-  }
-
-  /* bss segment */
-  .sbss : {
-    *(.sbss .sbss.* .gnu.linkonce.sb.*)
-    *(.scommon)
-  }
-  .bss : { *(.bss) }
-
-  __malloc_start = .;
-  . = . + 512;
-
-  /* End of uninitalized data segement */
-  _end = .;
-}
diff --git a/debug/targets/freedom-e300/openocd.cfg b/debug/targets/freedom-e300/openocd.cfg
deleted file mode 100644
index 87c977a..0000000
--- a/debug/targets/freedom-e300/openocd.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-adapter_khz     10000
-
-source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
-
-gdb_report_data_abort enable
-
-init
-
-halt
-echo "Ready for Remote Connections"
diff --git a/debug/targets/freedom-u500-sim/link.lds b/debug/targets/freedom-u500-sim/link.lds
deleted file mode 100755
index 1e0645a..0000000
--- a/debug/targets/freedom-u500-sim/link.lds
+++ /dev/null
@@ -1,34 +0,0 @@
-OUTPUT_ARCH( "riscv" )
-
-SECTIONS
-{
-  . = 0x80000000;
-  .text : 
-  {
-    *(.text.entry)
-    *(.text)
-  }
-
-  /* data segment */
-  .data : { *(.data) }
-
-  .sdata : {
-    __global_pointer$ = . + 0x800;
-    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
-    *(.srodata*)
-    *(.sdata .sdata.* .gnu.linkonce.s.*)
-  }
-
-  /* bss segment */
-  .sbss : {
-    *(.sbss .sbss.* .gnu.linkonce.sb.*)
-    *(.scommon)
-  }
-  .bss : { *(.bss) }
-
-  __malloc_start = .;
-  . = . + 512;
-
-  /* End of uninitalized data segement */
-  _end = .;
-}
diff --git a/debug/targets/freedom-u500-sim/openocd.cfg b/debug/targets/freedom-u500-sim/openocd.cfg
deleted file mode 100644
index 5fba211..0000000
--- a/debug/targets/freedom-u500-sim/openocd.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-adapter_khz     10000
-
-source [find interface/jtag_vpi.cfg]
-jtag_vpi_set_port $::env(JTAG_VPI_PORT)
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
-
-init
-
-halt
-echo "Ready for Remote Connections"
diff --git a/debug/targets/freedom-u500/link.lds b/debug/targets/freedom-u500/link.lds
deleted file mode 100755
index 1e0645a..0000000
--- a/debug/targets/freedom-u500/link.lds
+++ /dev/null
@@ -1,34 +0,0 @@
-OUTPUT_ARCH( "riscv" )
-
-SECTIONS
-{
-  . = 0x80000000;
-  .text : 
-  {
-    *(.text.entry)
-    *(.text)
-  }
-
-  /* data segment */
-  .data : { *(.data) }
-
-  .sdata : {
-    __global_pointer$ = . + 0x800;
-    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
-    *(.srodata*)
-    *(.sdata .sdata.* .gnu.linkonce.s.*)
-  }
-
-  /* bss segment */
-  .sbss : {
-    *(.sbss .sbss.* .gnu.linkonce.sb.*)
-    *(.scommon)
-  }
-  .bss : { *(.bss) }
-
-  __malloc_start = .;
-  . = . + 512;
-
-  /* End of uninitalized data segement */
-  _end = .;
-}