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| author | Tim Newsome <tim@sifive.com> | 2017-08-10 11:43:49 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-08-10 11:43:49 -0700 |
| commit | d44ebb21c0131c661575539771a1d97fc9afa4c1 (patch) | |
| tree | 2c0b0ee2210e50b061a9e06f1fc8383fb7e33b79 /debug/targets/SiFive | |
| parent | 130702297a010b4a2e7452bb48f0da88c0b30aa9 (diff) | |
| download | riscv-tests-d44ebb21c0131c661575539771a1d97fc9afa4c1.zip riscv-tests-d44ebb21c0131c661575539771a1d97fc9afa4c1.tar.gz riscv-tests-d44ebb21c0131c661575539771a1d97fc9afa4c1.tar.bz2 | |
Give these sim targets a chance of passing.
Also make sure vsim.log makes it into the generated log file.
Diffstat (limited to 'debug/targets/SiFive')
| -rw-r--r-- | debug/targets/SiFive/Freedom/E300Sim.py | 3 | ||||
| -rw-r--r-- | debug/targets/SiFive/Freedom/U500Sim.py | 7 |
2 files changed, 7 insertions, 3 deletions
diff --git a/debug/targets/SiFive/Freedom/E300Sim.py b/debug/targets/SiFive/Freedom/E300Sim.py index e98c5b9..91be2e8 100644 --- a/debug/targets/SiFive/Freedom/E300Sim.py +++ b/debug/targets/SiFive/Freedom/E300Sim.py @@ -1,4 +1,5 @@ import targets +import testlib class E300Sim(targets.Target): xlen = 32 @@ -9,5 +10,5 @@ class E300Sim(targets.Target): openocd_config_path = "Freedom.cfg" link_script_path = "Freedom.lds" - def target(self): + def create(self): return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False) diff --git a/debug/targets/SiFive/Freedom/U500Sim.py b/debug/targets/SiFive/Freedom/U500Sim.py index 7648960..62bc827 100644 --- a/debug/targets/SiFive/Freedom/U500Sim.py +++ b/debug/targets/SiFive/Freedom/U500Sim.py @@ -1,4 +1,7 @@ -class U500Sim(Target): +import targets +import testlib + +class U500Sim(targets.Target): xlen = 64 timeout_sec = 6000 ram = 0x80000000 @@ -7,5 +10,5 @@ class U500Sim(Target): openocd_config_path = "Freedom.cfg" link_script_path = "Freedom.lds" - def target(self): + def create(self): return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False) |