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| author | Tim Newsome <tim@sifive.com> | 2018-03-01 15:05:45 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2018-03-01 15:05:45 -0800 |
| commit | 208298c733a0e5ba9e4f7f892123745bdc7156c1 (patch) | |
| tree | 6cb350b713f7e5c50d8836a0e61feb442b797bbe /debug/targets/SiFive | |
| parent | 8f9f628b84826b7fbd1d91b24c56f634cef91cf4 (diff) | |
| download | riscv-tests-208298c733a0e5ba9e4f7f892123745bdc7156c1.zip riscv-tests-208298c733a0e5ba9e4f7f892123745bdc7156c1.tar.gz riscv-tests-208298c733a0e5ba9e4f7f892123745bdc7156c1.tar.bz2 | |
Ensure an error when reading a non-existent CSR.
Diffstat (limited to 'debug/targets/SiFive')
| -rw-r--r-- | debug/targets/SiFive/HiFive1.cfg | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/debug/targets/SiFive/HiFive1.cfg b/debug/targets/SiFive/HiFive1.cfg index 5bde59b..8f21b47 100644 --- a/debug/targets/SiFive/HiFive1.cfg +++ b/debug/targets/SiFive/HiFive1.cfg @@ -17,6 +17,10 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1 #-rtos riscv +# Expose an unimplemented CSR so we can test non-existent register access +# behavior. +riscv expose_csrs 2288 + flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME init #reset |