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| author | Tim Newsome <tim@sifive.com> | 2017-12-27 15:41:45 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-12-27 15:43:02 -0800 |
| commit | d359b6252eceb5e28f1048591750954d09efd12b (patch) | |
| tree | 129881b104a3dc296aba35a29502b966c9feffdf /debug/targets/RISC-V/spike64.py | |
| parent | ffa920340430f62e767fb2397f4ee41ffaf441ce (diff) | |
| download | riscv-tests-d359b6252eceb5e28f1048591750954d09efd12b.zip riscv-tests-d359b6252eceb5e28f1048591750954d09efd12b.tar.gz riscv-tests-d359b6252eceb5e28f1048591750954d09efd12b.tar.bz2 | |
Test FPRs that aren't XLEN in size.
Cover all combinations of 32,64 bit XLEN with F and FD extensions.
Finishes Issue https://github.com/riscv/riscv-openocd/issues/110
Diffstat (limited to 'debug/targets/RISC-V/spike64.py')
| -rw-r--r-- | debug/targets/RISC-V/spike64.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py index 2cd67a5..2aa1dd0 100644 --- a/debug/targets/RISC-V/spike64.py +++ b/debug/targets/RISC-V/spike64.py @@ -15,4 +15,5 @@ class spike64(targets.Target): timeout_sec = 30 def create(self): - return testlib.Spike(self) + # 32-bit FPRs only + return testlib.Spike(self, isa="RV64IMAFC") |