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| author | Tim Newsome <tim@sifive.com> | 2017-09-21 15:19:47 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-09-21 15:19:47 -0700 |
| commit | 35c41f1391b51d4d9c4e0ab40fdfc45dbea346b2 (patch) | |
| tree | ea793ff318c16acb13a1b21063fd9544786bbba6 /debug/targets/RISC-V/spike32-2.py | |
| parent | fcd0e956339560021e2a16a143697b8123f227d6 (diff) | |
| download | riscv-tests-35c41f1391b51d4d9c4e0ab40fdfc45dbea346b2.zip riscv-tests-35c41f1391b51d4d9c4e0ab40fdfc45dbea346b2.tar.gz riscv-tests-35c41f1391b51d4d9c4e0ab40fdfc45dbea346b2.tar.bz2 | |
Add coverage for single-core non-rtos OpenOCD.
Diffstat (limited to 'debug/targets/RISC-V/spike32-2.py')
| -rw-r--r-- | debug/targets/RISC-V/spike32-2.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py index 6cf558d..a7b9a1c 100644 --- a/debug/targets/RISC-V/spike32-2.py +++ b/debug/targets/RISC-V/spike32-2.py @@ -5,7 +5,7 @@ import spike32 # pylint: disable=import-error class spike32_2(targets.Target): harts = [spike32.spike32_hart(), spike32.spike32_hart()] - openocd_config_path = "spike.cfg" + openocd_config_path = "spike-rtos.cfg" timeout_sec = 30 def create(self): |