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| author | Tim Newsome <tim@sifive.com> | 2017-06-22 18:37:55 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-06-22 18:37:55 -0700 |
| commit | 806deb8e53e029df31defc88d09c6c2c2b08e8f3 (patch) | |
| tree | a3398c2fffaadc24296f245a7e69356a22e4b466 /debug/programs | |
| parent | 9ff4594d26f485495f47d4473905af9c4f10caa8 (diff) | |
| download | riscv-tests-806deb8e53e029df31defc88d09c6c2c2b08e8f3.zip riscv-tests-806deb8e53e029df31defc88d09c6c2c2b08e8f3.tar.gz riscv-tests-806deb8e53e029df31defc88d09c6c2c2b08e8f3.tar.bz2 | |
Add basic multicore test.
Diffstat (limited to 'debug/programs')
| -rw-r--r-- | debug/programs/infinite_loop.S | 69 |
1 files changed, 36 insertions, 33 deletions
diff --git a/debug/programs/infinite_loop.S b/debug/programs/infinite_loop.S index 4b83143..6f15f45 100644 --- a/debug/programs/infinite_loop.S +++ b/debug/programs/infinite_loop.S @@ -1,40 +1,43 @@ #include "encoding.h" .global main + .global main_end + .global main_post_csrr // Load constants into all registers so we can test no register are // clobbered after attaching. main: - csrr x1, CSR_MISA - slli x2, x1, 1 - slli x3, x2, 1 - slli x4, x3, 1 - slli x5, x4, 1 - slli x6, x5, 1 - slli x7, x6, 1 - slli x8, x7, 1 - slli x9, x8, 1 - slli x10, x9, 1 - slli x11, x10, 1 - slli x12, x11, 1 - slli x13, x12, 1 - slli x14, x13, 1 - slli x15, x14, 1 - slli x16, x15, 1 - slli x17, x16, 1 - slli x18, x17, 1 - slli x19, x18, 1 - slli x20, x19, 1 - slli x21, x20, 1 - slli x22, x21, 1 - slli x23, x22, 1 - slli x24, x23, 1 - slli x25, x24, 1 - slli x26, x25, 1 - slli x27, x26, 1 - slli x28, x27, 1 - slli x29, x28, 1 - slli x30, x29, 1 - slli x31, x30, 1 -1: - j 1b + csrr x1, CSR_MHARTID +main_post_csrr: + addi x2, x1, 1 + addi x3, x2, 1 + addi x4, x3, 1 + addi x5, x4, 1 + addi x6, x5, 1 + addi x7, x6, 1 + addi x8, x7, 1 + addi x9, x8, 1 + addi x10, x9, 1 + addi x11, x10, 1 + addi x12, x11, 1 + addi x13, x12, 1 + addi x14, x13, 1 + addi x15, x14, 1 + addi x16, x15, 1 + addi x17, x16, 1 + addi x18, x17, 1 + addi x19, x18, 1 + addi x20, x19, 1 + addi x21, x20, 1 + addi x22, x21, 1 + addi x23, x22, 1 + addi x24, x23, 1 + addi x25, x24, 1 + addi x26, x25, 1 + addi x27, x26, 1 + addi x28, x27, 1 + addi x29, x28, 1 + addi x30, x29, 1 + addi x31, x30, 1 +main_end: + j main |