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| author | Tim Newsome <tim@sifive.com> | 2017-06-26 10:00:34 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-06-26 10:06:10 -0700 |
| commit | 272e12eb177c662826f901d536f685a4abf62123 (patch) | |
| tree | 1a92b0969a5ed9ac60d62926d7c94222bdde069a /debug/Makefile | |
| parent | 806deb8e53e029df31defc88d09c6c2c2b08e8f3 (diff) | |
| download | riscv-tests-272e12eb177c662826f901d536f685a4abf62123.zip riscv-tests-272e12eb177c662826f901d536f685a4abf62123.tar.gz riscv-tests-272e12eb177c662826f901d536f685a4abf62123.tar.bz2 | |
Move target definition into individual files.
Instead of defining each target in targets.py, now each target gets its
own .py file. This means people can easily keep their own target files
around that they may not want to put into the main test source. As part
of that, I removed the freedom-u500-sim target since I assume it's only
used internally at SiFive.
Added a few cleanups as well:
* Update README examples, mostly --sim_cmd instead of --cmd.
* Allow defining misa in a target, to skip running of ExamineTarget.
* Rename target.target() to target.create(), which is less confusing.
* Default --sim_cmd to `spike`
* Got rid of `use_fpu`, instead looking at F or D in $misa.
Diffstat (limited to 'debug/Makefile')
| -rw-r--r-- | debug/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/debug/Makefile b/debug/Makefile index f835507..c5ea991 100644 --- a/debug/Makefile +++ b/debug/Makefile @@ -14,7 +14,7 @@ pylint: %.log: $(GDBSERVER_PY) \ --isolate \ - --$(subst .log,,$@) \ + targets/RISC-V/$(subst .log,.py,$@) \ --sim_cmd $(RISCV)/bin/$(RISCV_SIM) \ --server_cmd $(RISCV)/bin/openocd \ | tee $@ 2>&1 || (sed s/^/$@:\ / $@ && false) |