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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-06-17 21:06:37 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-06-17 21:06:37 -0700 |
| commit | 26cfab585c781f06e977800000efe097dee4613d (patch) | |
| tree | b8aa343031fadcaa61dfa66c58b3f3de93614a9a | |
| parent | 0c4cfe09da4c66c70eec7de680c9612fe9aa3e4a (diff) | |
| download | riscv-tests-26cfab585c781f06e977800000efe097dee4613d.zip riscv-tests-26cfab585c781f06e977800000efe097dee4613d.tar.gz riscv-tests-26cfab585c781f06e977800000efe097dee4613d.tar.bz2 | |
Fix breakpoint test when only one breakpoint present
| -rw-r--r-- | isa/rv64mi/breakpoint.S | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S index 848435e..77c9509 100644 --- a/isa/rv64mi/breakpoint.S +++ b/isa/rv64mi/breakpoint.S @@ -16,7 +16,7 @@ RVTEST_CODE_BEGIN # Set up breakpoint to trap on M-mode fetches. li TESTNUM, 2 - # Skip tdrselect is hard-wired. + # Skip tdrselect if hard-wired. li a0, 1<<(_RISCV_SZLONG-1) csrw tdrselect, a0 csrr a1, tdrselect @@ -87,6 +87,13 @@ RVTEST_CODE_BEGIN csrw tdrselect, a0 csrr a1, tdrselect bne a0, a1, pass + + # Make sure there's a breakpoint there. + csrr a0, tdrdata1 + srli a0, a0, _RISCV_SZLONG-4 + li a1, 1 + bne a0, a1, pass + li a0, BPCONTROL_M | BPCONTROL_R csrw tdrdata1, a0 la a3, data2 |