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| author | Megan Wachs <megan@sifive.com> | 2017-05-18 12:14:07 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-05-18 12:14:07 -0700 |
| commit | 5ff7b723976b3736daa0f0ad5df71d40576a674a (patch) | |
| tree | 9a356049eecc480d8910c75f56b1a8db06a8538e | |
| parent | 019192fead976af698d16b090d75be2dc7da053e (diff) | |
| parent | d74b266e4fa780ec0b42663b752deaa58fda91ae (diff) | |
| download | riscv-tests-5ff7b723976b3736daa0f0ad5df71d40576a674a.zip riscv-tests-5ff7b723976b3736daa0f0ad5df71d40576a674a.tar.gz riscv-tests-5ff7b723976b3736daa0f0ad5df71d40576a674a.tar.bz2 | |
Merge pull request #52 from riscv/vcs_sim_cmd
debug: Correct the calling for a 32-bit simulation target
| -rw-r--r-- | debug/targets.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/debug/targets.py b/debug/targets.py index 423ff69..b8557ce 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -107,7 +107,7 @@ class FreedomE300SimTarget(Target): openocd_config = "targets/%s/openocd.cfg" % name def target(self): - return testlib.VcsSim(simv=self.sim_cmd, debug=False) + return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False) class FreedomU500Target(Target): name = "freedom-u500" |