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| author | Megan Wachs <megan@sifive.com> | 2017-05-15 00:54:41 -0700 |
|---|---|---|
| committer | Megan Wachs <megan@sifive.com> | 2017-05-15 00:54:41 -0700 |
| commit | 46fdf4920da71f3f8690349d72fe6a516fd97735 (patch) | |
| tree | e965212f5d42061b4b784a88e26008e3c469cb02 | |
| parent | 201fc773aef7f93107cbe098b9531ba6e18cd913 (diff) | |
| download | riscv-tests-46fdf4920da71f3f8690349d72fe6a516fd97735.zip riscv-tests-46fdf4920da71f3f8690349d72fe6a516fd97735.tar.gz riscv-tests-46fdf4920da71f3f8690349d72fe6a516fd97735.tar.bz2 | |
debug: Use consistent 'sim_cmd' argument.
| -rw-r--r-- | debug/targets.py | 2 | ||||
| -rw-r--r-- | debug/testlib.py | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/debug/targets.py b/debug/targets.py index a69f43d..17e752d 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -127,7 +127,7 @@ class FreedomU500SimTarget(Target): openocd_config = "targets/%s/openocd.cfg" % name def target(self): - return testlib.VcsSim(simv=self.sim_cmd, debug=False) + return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False) targets = [ Spike32Target, diff --git a/debug/testlib.py b/debug/testlib.py index a66d59a..df976df 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -113,7 +113,7 @@ class Spike(object): class VcsSim(object): def __init__(self, sim_cmd=None, debug=False): if sim_cmd: - cmd = shlex.split(simv) + cmd = shlex.split(sim_cmd) else: cmd = ["simv"] cmd += ["+jtag_vpi_enable"] |