Test simultaneous resume using hasel. (#186)

Passes on spike and Arty. Won't merge until
https://github.com/riscv/riscv-openocd/pull/364 merges.

9 files changed, 51 insertions, 31 deletions

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index e7f0701..754c560 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -843,10 +843,10 @@ class MulticoreRtosSwitchActiveHartTest(GdbTest):
             assertNotIn("received signal SIGTRAP", output)
 
 class SmpSimultaneousRunHalt(GdbTest):
-    compile_args = ("programs/run_halt_timing.c", "-DMULTICORE")
+    compile_args = ("programs/run_halt_timing.S", "-DMULTICORE")
 
     def early_applicable(self):
-        return len(self.target.harts) > 1
+        return len(self.target.harts) > 1 and self.target.support_hasel
 
     def setup(self):
         self.gdb.select_hart(self.target.harts[0])
@@ -869,15 +869,16 @@ class SmpSimultaneousRunHalt(GdbTest):
             counter = []
             for hart in self.target.harts:
                 self.gdb.select_hart(hart)
-                mv = self.gdb.p("mtime_value")
+                mv = self.gdb.p("$s2")
                 assertNotIn(mv, old_mtime,
                         "mtime doesn't appear to be changing at all")
                 mtime_value.append(mv)
-                c = self.gdb.p("counter")
+                c = self.gdb.p("$s0")
                 assertNotEqual(c, 0,
                         "counter didn't increment; code didn't run?")
                 counter.append(c)
-                self.gdb.p("counter=0")
+                # Reset the counter for the next round.
+                self.gdb.p("$s0=0")
 
             old_mtime.update(mtime_value)
 
@@ -886,10 +887,14 @@ class SmpSimultaneousRunHalt(GdbTest):
             counter_spread = max(counter) - min(counter)
             print "counter_spread:", counter_spread
 
-            assertLess(mtime_spread, 100 * len(self.target.harts),
+            assertLess(mtime_spread, 101 * (len(self.target.harts) - 1),
                     "Harts don't halt around the same time.")
-#TODO            assertLess(counter_spread, 100 * len(self.target.harts),
-#TODO                    "Harts don't resume around the same time.")
+            # spike executes normal code 5000 instructions at a time, so we
+            # expect 5k instructions to be executed on one hart before the
+            # other gets to go. Our loop (unoptimized) is quite a few
+            # instructions, but allow for 5k anyway.
+            assertLess(counter_spread, 5001 * (len(self.target.harts) - 1),
+                    "Harts don't resume around the same time.")
 
 class StepTest(GdbSingleHartTest):
     compile_args = ("programs/step.S", )
diff --git a/debug/programs/run_halt_timing.S b/debug/programs/run_halt_timing.S
new file mode 100644
index 0000000..ce4000a
--- /dev/null
+++ b/debug/programs/run_halt_timing.S
@@ -0,0 +1,18 @@
+#if XLEN == 64
+# define LREG ld
+# define SREG sd
+# define REGBYTES 8
+#else
+# define LREG lw
+# define SREG sw
+# define REGBYTES 4
+#endif
+
+        .global main
+main:
+        li      s0, 0
+        li      s1, 0x0200bff8
+loop:
+        addi    s0, s0, 1
+        LREG    s2, 0(s1)
+        j       loop
diff --git a/debug/programs/run_halt_timing.c b/debug/programs/run_halt_timing.c
deleted file mode 100644
index 1c9a8ba..0000000
--- a/debug/programs/run_halt_timing.c
+++ /dev/null
@@ -1,17 +0,0 @@
-#include <stdio.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-
-#include "init.h"
-
-int main()
-{
-    int counter = 0;
-    volatile uint64_t mtime_value;
-
-    while (1) {
-        counter = counter + 1;
-        mtime_value = MTIME;
-    }
-}
diff --git a/debug/targets.py b/debug/targets.py
index 5d7976b..b686b2a 100644
--- a/debug/targets.py
+++ b/debug/targets.py
@@ -82,6 +82,9 @@ class Target(object):
     # When true it indicates that reading invalid memory doesn't return an error
     invalid_memory_returns_zero = False
 
+    # Supports simultaneous resume through hasel.
+    support_hasel = True
+
     # Internal variables:
     directory = None
     temporary_files = []
diff --git a/debug/targets/RISC-V/spike32-2-hwthread.py b/debug/targets/RISC-V/spike32-2-hwthread.py
index bec68dc..333a7f2 100644
--- a/debug/targets/RISC-V/spike32-2-hwthread.py
+++ b/debug/targets/RISC-V/spike32-2-hwthread.py
@@ -8,6 +8,7 @@ class spike32_2(targets.Target):
     openocd_config_path = "spike-2-hwthread.cfg"
     timeout_sec = 5
     implements_custom_test = True
+    support_hasel = False
 
     def create(self):
-        return testlib.Spike(self)
+        return testlib.Spike(self, support_hasel=False)
diff --git a/debug/targets/RISC-V/spike32-2-rtos.py b/debug/targets/RISC-V/spike32-2-rtos.py
index a2951c1..4b29801 100644
--- a/debug/targets/RISC-V/spike32-2-rtos.py
+++ b/debug/targets/RISC-V/spike32-2-rtos.py
@@ -8,6 +8,8 @@ class spike32_2(targets.Target):
     openocd_config_path = "spike-rtos.cfg"
     timeout_sec = 30
     implements_custom_test = True
+    support_hasel = False
 
     def create(self):
-        return testlib.Spike(self, progbufsize=0, dmi_rti=4)
+        return testlib.Spike(self, progbufsize=0, dmi_rti=4,
+                support_hasel=False)
diff --git a/debug/targets/RISC-V/spike64-2-rtos.py b/debug/targets/RISC-V/spike64-2-rtos.py
index 1da7116..3e7c221 100644
--- a/debug/targets/RISC-V/spike64-2-rtos.py
+++ b/debug/targets/RISC-V/spike64-2-rtos.py
@@ -8,6 +8,7 @@ class spike64_2_rtos(targets.Target):
     openocd_config_path = "spike-rtos.cfg"
     timeout_sec = 60
     implements_custom_test = True
+    support_hasel = False
 
     def create(self):
-        return testlib.Spike(self, abstract_rti=30)
+        return testlib.Spike(self, abstract_rti=30, support_hasel=False)
diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py
index e981105..beccae3 100644
--- a/debug/targets/RISC-V/spike64-2.py
+++ b/debug/targets/RISC-V/spike64-2.py
@@ -6,8 +6,10 @@ import spike64  # pylint: disable=import-error
 class spike64_2(targets.Target):
     harts = [spike64.spike64_hart(), spike64.spike64_hart()]
     openocd_config_path = "spike-2.cfg"
-    timeout_sec = 60
+    timeout_sec = 10
     implements_custom_test = True
+    support_hasel = False
 
     def create(self):
-        return testlib.Spike(self, isa="RV64IMAFD", abstract_rti=30)
+        return testlib.Spike(self, isa="RV64IMAFD", abstract_rti=30,
+                support_hasel=False)
diff --git a/debug/testlib.py b/debug/testlib.py
index c4b785c..b3163c3 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -58,7 +58,8 @@ def compile(args, xlen=32): # pylint: disable=redefined-builtin
 class Spike(object):
     # pylint: disable=too-many-instance-attributes
     def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True,
-            isa=None, progbufsize=None, dmi_rti=None, abstract_rti=None):
+            isa=None, progbufsize=None, dmi_rti=None, abstract_rti=None,
+            support_hasel=True):
         """Launch spike. Return tuple of its process and the port it's running
         on."""
         self.process = None
@@ -66,6 +67,7 @@ class Spike(object):
         self.progbufsize = progbufsize
         self.dmi_rti = dmi_rti
         self.abstract_rti = abstract_rti
+        self.support_hasel = support_hasel
 
         if target.harts:
             harts = target.harts
@@ -133,6 +135,9 @@ class Spike(object):
         if not self.abstract_rti is None:
             cmd += ["--abstract-rti", str(self.abstract_rti)]
 
+        if not self.support_hasel:
+            cmd.append("--without-hasel")
+
         assert len(set(t.ram for t in harts)) == 1, \
                 "All spike harts must have the same RAM layout"
         assert len(set(t.ram_size for t in harts)) == 1, \