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| author | Andrew Waterman <waterman@eecs.berkeley.edu> | 2013-06-10 00:55:35 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2013-06-10 00:55:35 -0700 |
| commit | 4412b96c81ca09dcce6305579dd86d4bf3b808da (patch) | |
| tree | 4a43c10dae33a5986029eb4fb4fa8f11c8c93e75 | |
| parent | c4e3da6be335f85482c1cbd85b6c507c48652bc8 (diff) | |
| download | riscv-tests-4412b96c81ca09dcce6305579dd86d4bf3b808da.zip riscv-tests-4412b96c81ca09dcce6305579dd86d4bf3b808da.tar.gz riscv-tests-4412b96c81ca09dcce6305579dd86d4bf3b808da.tar.bz2 | |
Don't disassemble zeros
It's gratuitous.
| -rw-r--r-- | isa/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/isa/Makefile b/isa/Makefile index 77a0407..3abb3b1 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -17,7 +17,7 @@ default: all RISCV_GCC = riscv-gcc RISCV_GCC_OPTS = -nostdlib -nostartfiles -RISCV_OBJDUMP = riscv-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.data --section=.bss +RISCV_OBJDUMP = riscv-objdump --disassemble-all --section=.text --section=.data --section=.bss RISCV_SIM = spike #------------------------------------------------------------ |