Test FPRs that aren't XLEN in size.

Cover all combinations of 32,64 bit XLEN with F and FD extensions.

Finishes Issue https://github.com/riscv/riscv-openocd/issues/110

6 files changed, 20 insertions, 8 deletions

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index d7092a8..8104fed 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -121,6 +121,12 @@ class SimpleF18Test(SimpleRegisterTest):
             self.gdb.stepi()
             assertLess(abs(float(self.gdb.p_raw("$%s" % name)) - b), .001)
             assertLess(abs(float(self.gdb.p_raw("$%s" % alias)) - b), .001)
+
+            size = self.gdb.p("sizeof($%s)" % name)
+            if self.hart.extensionSupported('D'):
+                assertEqual(size, 8)
+            else:
+                assertEqual(size, 4)
         else:
             output = self.gdb.p_raw("$" + name)
             assertEqual(output, "void")
diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py
index 719009d..f57f816 100644
--- a/debug/targets/RISC-V/spike32-2.py
+++ b/debug/targets/RISC-V/spike32-2.py
@@ -9,4 +9,4 @@ class spike32_2(targets.Target):
     timeout_sec = 30
 
     def create(self):
-        return testlib.Spike(self)
+        return testlib.Spike(self, isa="RV32IMAFC")
diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py
index 809463c..dfcfc01 100644
--- a/debug/targets/RISC-V/spike32.py
+++ b/debug/targets/RISC-V/spike32.py
@@ -15,4 +15,5 @@ class spike32(targets.Target):
     timeout_sec = 30
 
     def create(self):
-        return testlib.Spike(self)
+        # 64-bit FPRs on 32-bit target
+        return testlib.Spike(self, isa="RV32IMAFDC")
diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py
index 79aab3e..a2082b4 100644
--- a/debug/targets/RISC-V/spike64-2.py
+++ b/debug/targets/RISC-V/spike64-2.py
@@ -9,4 +9,4 @@ class spike64_2(targets.Target):
     timeout_sec = 60
 
     def create(self):
-        return testlib.Spike(self)
+        return testlib.Spike(self, isa="RV64IMAFD")
diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py
index 2cd67a5..2aa1dd0 100644
--- a/debug/targets/RISC-V/spike64.py
+++ b/debug/targets/RISC-V/spike64.py
@@ -15,4 +15,5 @@ class spike64(targets.Target):
     timeout_sec = 30
 
     def create(self):
-        return testlib.Spike(self)
+        # 32-bit FPRs only
+        return testlib.Spike(self, isa="RV64IMAFC")
diff --git a/debug/testlib.py b/debug/testlib.py
index ce8aeca..94ee83e 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -56,10 +56,12 @@ def compile(args, xlen=32): # pylint: disable=redefined-builtin
         raise Exception("Compile failed!")
 
 class Spike(object):
-    def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True):
+    def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True,
+            isa=None):
         """Launch spike. Return tuple of its process and the port it's running
         on."""
         self.process = None
+        self.isa = isa
 
         if target.harts:
             harts = target.harts
@@ -109,10 +111,12 @@ class Spike(object):
         assert len(set(t.xlen for t in harts)) == 1, \
                 "All spike harts must have the same XLEN"
 
-        if harts[0].xlen == 32:
-            cmd += ["--isa", "RV32G"]
+        if self.isa:
+            isa = self.isa
         else:
-            cmd += ["--isa", "RV64G"]
+            isa = "RV%dG" % harts[0].xlen
+
+        cmd += ["--isa", isa]
 
         assert len(set(t.ram for t in harts)) == 1, \
                 "All spike harts must have the same RAM layout"