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| author | Andrew Waterman <andrew@sifive.com> | 2017-11-09 17:12:49 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-11-09 19:26:41 -0800 |
| commit | 652ec8c0c98bfc64bbc8d036d89c61066aebee91 (patch) | |
| tree | c7dad126543ec4a9b8f5159f9dedda7977a6f9b8 | |
| parent | 6f7ebb610d6bb8817a9592cc06a7d108381f1761 (diff) | |
| download | riscv-tests-652ec8c0c98bfc64bbc8d036d89c61066aebee91.zip riscv-tests-652ec8c0c98bfc64bbc8d036d89c61066aebee91.tar.gz riscv-tests-652ec8c0c98bfc64bbc8d036d89c61066aebee91.tar.bz2 | |
Use mstatus.MPP to check existence of U-mode
misa is allowed to be hardwired to 0, so checking its U bit could
incorrectly suggest that U-mode is not supported.
| -rw-r--r-- | isa/rv64si/csr.S | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S index 5a8edbe..dbe1c05 100644 --- a/isa/rv64si/csr.S +++ b/isa/rv64si/csr.S @@ -26,13 +26,14 @@ RVTEST_CODE_BEGIN # For RV64, make sure UXL encodes RV64. (UXL does not exist for RV32.) #if __riscv_xlen == 64 - # If running in M mode, read misa to check existence of U mode. + # If running in M mode, use mstatus.MPP to check existence of U mode. # Otherwise, if in S mode, then U mode must exist and we don't need to check. #ifdef __MACHINE_MODE - csrr a0, misa - srli a0, a0, 'U' - 'A' - andi a0, a0, 1 - beqz a0, 1f + li t0, MSTATUS_MPP + csrc mstatus, t0 + csrr t1, mstatus + and t0, t0, t1 + bnez t0, 1f #endif # If U mode is present, UXL should be 2 (XLEN = 64-bit) TEST_CASE(13, a0, SSTATUS_UXL & (SSTATUS_UXL << 1), csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1) |