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author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-05-18 14:35:32 -0700 |
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committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-05-18 14:35:32 -0700 |
commit | 92a8f05f5a2081deb086ad478c3ecbfd4e649002 (patch) | |
tree | f381f5cd4e2e6be751dabac6fc096a0813f14707 /pk | |
parent | bbd999a00eb4859576db2422ceefc0ebf6d721e5 (diff) | |
download | riscv-pk-92a8f05f5a2081deb086ad478c3ecbfd4e649002.zip riscv-pk-92a8f05f5a2081deb086ad478c3ecbfd4e649002.tar.gz riscv-pk-92a8f05f5a2081deb086ad478c3ecbfd4e649002.tar.bz2 |
[opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)
Diffstat (limited to 'pk')
-rw-r--r-- | pk/handlers.c | 14 | ||||
-rw-r--r-- | pk/pcr.h | 4 |
2 files changed, 17 insertions, 1 deletions
diff --git a/pk/handlers.c b/pk/handlers.c index 3634135..ebc8f2a 100644 --- a/pk/handlers.c +++ b/pk/handlers.c @@ -12,6 +12,18 @@ static void handle_vector_disabled(trapframe_t* tf) panic("No vector hardware! pc %lx, insn %x",tf->epc,(uint32_t)tf->insn); } +static void handle_vector_bank(trapframe_t* tf) +{ + dump_tf(tf); + panic("Not enought banks were enabled to execute a vector instruction!"); +} + +static void handle_vector_illegal_instruction(trapframe_t* tf) +{ + dump_tf(tf); + panic("An illegal vector instruction was executed!"); +} + static void handle_privileged_instruction(trapframe_t* tf) { dump_tf(tf); @@ -144,6 +156,8 @@ void handle_trap(trapframe_t* tf) [CAUSE_FAULT_LOAD] = handle_fault_load, [CAUSE_FAULT_STORE] = handle_fault_store, [CAUSE_VECTOR_DISABLED] = handle_vector_disabled, + [CAUSE_VECTOR_BANK] = handle_vector_bank, + [CAUSE_VECTOR_ILLEGAL_INSTRUCTION] = handle_vector_illegal_instruction, }; int exccode = (tf->cause & CAUSE_EXCCODE) >> CAUSE_EXCCODE_SHIFT; @@ -53,7 +53,9 @@ #define CAUSE_FAULT_LOAD 10 #define CAUSE_FAULT_STORE 11 #define CAUSE_VECTOR_DISABLED 12 -#define NUM_CAUSES 13 +#define CAUSE_VECTOR_BANK 13 +#define CAUSE_VECTOR_ILLEGAL_INSTRUCTION 14 +#define NUM_CAUSES 15 #define ASM_CR(r) _ASM_CR(r) #define _ASM_CR(r) $cr##r |