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author | Gabriel L. Somlo <gsomlo@gmail.com> | 2019-06-11 10:51:01 -0400 |
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committer | Gabriel L. Somlo <gsomlo@gmail.com> | 2019-06-11 10:55:53 -0400 |
commit | 9c20a7744f7ad070094af0c1c29346fcfec50829 (patch) | |
tree | b4ebec71f912e2a2359f86e244a950bb54422166 /machine | |
parent | cb253a3f970b373df4390a0e7a17610556f920f3 (diff) | |
download | riscv-pk-9c20a7744f7ad070094af0c1c29346fcfec50829.zip riscv-pk-9c20a7744f7ad070094af0c1c29346fcfec50829.tar.gz riscv-pk-9c20a7744f7ad070094af0c1c29346fcfec50829.tar.bz2 |
Check for 'U' extension before accessing 'mcounteren' CSR
On 64-bit Rocket with 'DefaultFPGAConfig' (using 'WithNSmallCores'),
the 'U' extension is not supported, and accessing 'mcounteren' would
trigger an 'Illegal Instruction' trap.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Diffstat (limited to 'machine')
-rw-r--r-- | machine/minit.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/machine/minit.c b/machine/minit.c index bb1ee6e..5ad6d92 100644 --- a/machine/minit.c +++ b/machine/minit.c @@ -30,7 +30,8 @@ static void mstatus_init() // Enable user/supervisor use of perf counters if (supports_extension('S')) write_csr(scounteren, -1); - write_csr(mcounteren, -1); + if (supports_extension('U')) + write_csr(mcounteren, -1); // Enable software interrupts write_csr(mie, MIP_MSIP); |