Separate page faults from physical memory access exceptions

5 files changed, 37 insertions, 21 deletions

diff --git a/machine/encoding.h b/machine/encoding.h
index 4f0d0a4..b07d976 100644
--- a/machine/encoding.h
+++ b/machine/encoding.h
@@ -147,9 +147,8 @@
 #define IRQ_HOST     13
 
 #define DEFAULT_RSTVEC     0x00001000
-#define DEFAULT_NMIVEC     0x00001004
-#define DEFAULT_MTVEC      0x00001010
-#define CONFIG_STRING_ADDR 0x0000100C
+#define CLINT_BASE         0x02000000
+#define CLINT_SIZE         0x000c0000
 #define EXT_IO_BASE        0x40000000
 #define DRAM_BASE          0x80000000
 
@@ -959,17 +958,20 @@
 #define CSR_MHPMCOUNTER30H 0xb9e
 #define CSR_MHPMCOUNTER31H 0xb9f
 #define CAUSE_MISALIGNED_FETCH 0x0
-#define CAUSE_FAULT_FETCH 0x1
+#define CAUSE_FETCH_ACCESS 0x1
 #define CAUSE_ILLEGAL_INSTRUCTION 0x2
 #define CAUSE_BREAKPOINT 0x3
 #define CAUSE_MISALIGNED_LOAD 0x4
-#define CAUSE_FAULT_LOAD 0x5
+#define CAUSE_LOAD_ACCESS 0x5
 #define CAUSE_MISALIGNED_STORE 0x6
-#define CAUSE_FAULT_STORE 0x7
+#define CAUSE_STORE_ACCESS 0x7
 #define CAUSE_USER_ECALL 0x8
 #define CAUSE_SUPERVISOR_ECALL 0x9
 #define CAUSE_HYPERVISOR_ECALL 0xa
 #define CAUSE_MACHINE_ECALL 0xb
+#define CAUSE_FETCH_PAGE_FAULT 0xc
+#define CAUSE_LOAD_PAGE_FAULT 0xd
+#define CAUSE_STORE_PAGE_FAULT 0xf
 #endif
 #ifdef DECLARE_INSN
 DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
@@ -1451,15 +1453,18 @@ DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
 #endif
 #ifdef DECLARE_CAUSE
 DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
-DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
+DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS)
 DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
 DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
 DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
-DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
+DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS)
 DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
-DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
+DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS)
 DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
 DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
 DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
 DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
+DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT)
+DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT)
+DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT)
 #endif
diff --git a/machine/mentry.S b/machine/mentry.S
index 9ce3257..9575dc9 100644
--- a/machine/mentry.S
+++ b/machine/mentry.S
@@ -8,19 +8,22 @@
 trap_table:
 #define BAD_TRAP_VECTOR 0
   .word bad_trap
-  .word bad_trap
+  .word pmp_trap
   .word illegal_insn_trap
   .word bad_trap
   .word misaligned_load_trap
-  .word bad_trap
+  .word pmp_trap
   .word misaligned_store_trap
-  .word bad_trap
+  .word pmp_trap
   .word bad_trap
   .word mcall_trap
   .word bad_trap
   .word bad_trap
-#define TRAP_FROM_MACHINE_MODE_VECTOR 12
+  .word bad_trap
+#define TRAP_FROM_MACHINE_MODE_VECTOR 13
   .word __trap_from_machine_mode
+  .word bad_trap
+  .word bad_trap
 
   .option norvc
   .section .text.init,"ax",@progbits
diff --git a/machine/minit.c b/machine/minit.c
index 7083b05..48366d7 100644
--- a/machine/minit.c
+++ b/machine/minit.c
@@ -35,10 +35,10 @@ static void delegate_traps()
   uintptr_t interrupts = MIP_SSIP | MIP_STIP | MIP_SEIP;
   uintptr_t exceptions =
     (1U << CAUSE_MISALIGNED_FETCH) |
-    (1U << CAUSE_FAULT_FETCH) |
+    (1U << CAUSE_FETCH_PAGE_FAULT) |
     (1U << CAUSE_BREAKPOINT) |
-    (1U << CAUSE_FAULT_LOAD) |
-    (1U << CAUSE_FAULT_STORE) |
+    (1U << CAUSE_LOAD_PAGE_FAULT) |
+    (1U << CAUSE_STORE_PAGE_FAULT) |
     (1U << CAUSE_BREAKPOINT) |
     (1U << CAUSE_USER_ECALL);
 
diff --git a/machine/mtrap.c b/machine/mtrap.c
index 15859d1..6e85d26 100644
--- a/machine/mtrap.c
+++ b/machine/mtrap.c
@@ -167,6 +167,11 @@ void redirect_trap(uintptr_t epc, uintptr_t mstatus)
   return __redirect_trap();
 }
 
+void pmp_trap(uintptr_t* regs, uintptr_t mcause, uintptr_t mepc)
+{
+  redirect_trap(mepc, read_csr(mstatus));
+}
+
 static void machine_page_fault(uintptr_t* regs, uintptr_t dummy, uintptr_t mepc)
 {
   // MPRV=1 iff this trap occurred while emulating an instruction on behalf
@@ -184,8 +189,11 @@ void trap_from_machine_mode(uintptr_t* regs, uintptr_t dummy, uintptr_t mepc)
 
   switch (mcause)
   {
-    case CAUSE_FAULT_LOAD:
-    case CAUSE_FAULT_STORE:
+    case CAUSE_LOAD_PAGE_FAULT:
+    case CAUSE_STORE_PAGE_FAULT:
+    case CAUSE_FETCH_ACCESS:
+    case CAUSE_LOAD_ACCESS:
+    case CAUSE_STORE_ACCESS:
       return machine_page_fault(regs, dummy, mepc);
     default:
       bad_trap(regs, dummy, mepc);
diff --git a/pk/handlers.c b/pk/handlers.c
index 1961852..b0eb76b 100644
--- a/pk/handlers.c
+++ b/pk/handlers.c
@@ -83,13 +83,13 @@ void handle_trap(trapframe_t* tf)
 
   const static trap_handler trap_handlers[] = {
     [CAUSE_MISALIGNED_FETCH] = handle_misaligned_fetch,
-    [CAUSE_FAULT_FETCH] = handle_fault_fetch,
+    [CAUSE_FETCH_PAGE_FAULT] = handle_fault_fetch,
     [CAUSE_ILLEGAL_INSTRUCTION] = handle_illegal_instruction,
     [CAUSE_USER_ECALL] = handle_syscall,
     [CAUSE_BREAKPOINT] = handle_breakpoint,
     [CAUSE_MISALIGNED_STORE] = handle_misaligned_store,
-    [CAUSE_FAULT_LOAD] = handle_fault_load,
-    [CAUSE_FAULT_STORE] = handle_fault_store,
+    [CAUSE_LOAD_PAGE_FAULT] = handle_fault_load,
+    [CAUSE_STORE_PAGE_FAULT] = handle_fault_store,
   };
 
   kassert(tf->cause < ARRAY_SIZE(trap_handlers) && trap_handlers[tf->cause]);