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| author | Alex Solomatnikov <sols@sifive.com> | 2018-04-05 10:03:51 -0700 |
|---|---|---|
| committer | Alex Solomatnikov <sols@sifive.com> | 2018-04-05 10:03:51 -0700 |
| commit | 08239bad26f06013971526447a0c50d2014244c0 (patch) | |
| tree | 187b2b059331987bdbc9dbd4a8bd44a35492f364 | |
| parent | 8cc6a045e7bf1eb1190b852a9866b8257f1fc10a (diff) | |
| download | riscv-pk-08239bad26f06013971526447a0c50d2014244c0.zip riscv-pk-08239bad26f06013971526447a0c50d2014244c0.tar.gz riscv-pk-08239bad26f06013971526447a0c50d2014244c0.tar.bz2 | |
Perf counter ids should be consistent with ISA spec
| -rw-r--r-- | machine/mtrap.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/machine/mtrap.c b/machine/mtrap.c index 13729be..3c10e66 100644 --- a/machine/mtrap.c +++ b/machine/mtrap.c @@ -97,8 +97,12 @@ static uintptr_t mcall_read_perf_cnt(uintptr_t id) switch (id) { case 0: - return read_csr(mhpmcounter3); + return read_csr(mcycle); case 1: + return read_csr(minstret); + case 2: + return read_csr(mhpmcounter3); + case 3: return read_csr(mhpmcounter4); } return -ENOSYS; @@ -108,10 +112,13 @@ static uintptr_t mcall_write_perf_cfg(uintptr_t id, uintptr_t val) { switch (id) { - case 0: + case 0: // mcycle - not configurable + case 1: // minstret - not configurable + return -ENOSYS; + case 3: write_csr(mhpmevent3, val); return 0; - case 1: + case 4: write_csr(mhpmevent4, val); return 0; } |