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| author | Palmer Dabbelt <palmer@dabbelt.com> | 2018-01-22 18:44:03 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-01-22 18:44:03 -0800 |
| commit | 2e03ddb03ab9a7ce416453d71923d4531e2f9fe6 (patch) | |
| tree | e6769534eafc9e398c8763737dddc651f2f690d0 | |
| parent | 3740bc51b3e3b526f9cfd7ae3dba7810b05d833d (diff) | |
| parent | 21dbf5f307b694a82e41e85e300ddbb37b275139 (diff) | |
| download | riscv-pk-2e03ddb03ab9a7ce416453d71923d4531e2f9fe6.zip riscv-pk-2e03ddb03ab9a7ce416453d71923d4531e2f9fe6.tar.gz riscv-pk-2e03ddb03ab9a7ce416453d71923d4531e2f9fe6.tar.bz2 | |
Merge pull request #76 from riscv/race
Boot on the first hart
| -rw-r--r-- | machine/mentry.S | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/machine/mentry.S b/machine/mentry.S index 11c053c..41d7017 100644 --- a/machine/mentry.S +++ b/machine/mentry.S @@ -257,15 +257,8 @@ do_reset: slli a2, a3, RISCV_PGSHIFT add sp, sp, a2 - # Boot on the first unmasked hart - la a4, disabled_hart_mask - LOAD a4, 0(a4) - addi a5, a4, 1 - not a4, a4 - and a4, a4, a5 - srl a4, a4, a3 - andi a4, a4, 1 - bnez a4, init_first_hart + # Boot on the first hart + beqz a3, init_first_hart # set MSIE bit to receive IPI li a2, MIP_MSIP |