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authorAndrew Waterman <andrew@sifive.com>2017-02-22 20:31:28 -0800
committerAndrew Waterman <andrew@sifive.com>2017-02-22 20:31:28 -0800
commit34979b93458d685df65a49bca3084eb8283439da (patch)
tree3c7cfa9b649f45ded8e7fabfad5e56bcd8488d39
parentf6bca6e35b66632afad68f6b7fb2b3203c8502fb (diff)
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Fix PK boot
-rw-r--r--machine/encoding.h22
-rw-r--r--machine/minit.c4
-rw-r--r--machine/vm.h4
-rw-r--r--pk/mmap.c9
4 files changed, 17 insertions, 22 deletions
diff --git a/machine/encoding.h b/machine/encoding.h
index 9a87807..e46e3d8 100644
--- a/machine/encoding.h
+++ b/machine/encoding.h
@@ -167,10 +167,12 @@
# define MSTATUS_SD MSTATUS64_SD
# define SSTATUS_SD SSTATUS64_SD
# define RISCV_PGLEVEL_BITS 9
+# define SPTBR_MODE SPTBR64_MODE
#else
# define MSTATUS_SD MSTATUS32_SD
# define SSTATUS_SD SSTATUS32_SD
# define RISCV_PGLEVEL_BITS 10
+# define SPTBR_MODE SPTBR32_MODE
#endif
#define RISCV_PGSHIFT 12
#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
@@ -184,30 +186,18 @@
__tmp; })
#define write_csr(reg, val) ({ \
- if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
- asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
- else \
- asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
+ asm volatile ("csrw " #reg ", %0" :: "rK"(val)); })
#define swap_csr(reg, val) ({ unsigned long __tmp; \
- if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
- asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
- else \
- asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \
__tmp; })
#define set_csr(reg, bit) ({ unsigned long __tmp; \
- if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
- asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
- else \
- asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
__tmp; })
#define clear_csr(reg, bit) ({ unsigned long __tmp; \
- if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
- asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
- else \
- asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
__tmp; })
#define rdtime() read_csr(time)
diff --git a/machine/minit.c b/machine/minit.c
index e84f6d9..0a1e37e 100644
--- a/machine/minit.c
+++ b/machine/minit.c
@@ -21,6 +21,9 @@ static void mstatus_init()
write_csr(mucounteren, -1);
write_csr(mscounteren, -1);
write_csr(mie, ~MIP_MTIP); // disable timer; enable other interrupts
+
+ // Disable paging
+ write_csr(sptbr, 0);
}
// send S-mode interrupts and most exceptions straight to S-mode
@@ -141,7 +144,6 @@ void enter_supervisor_mode(void (*fn)(uintptr_t), uintptr_t arg0, uintptr_t arg1
write_csr(mstatus, mstatus);
write_csr(mscratch, MACHINE_STACK_TOP() - MENTRY_FRAME_SIZE);
write_csr(mepc, fn);
- write_csr(sptbr, 0);
register uintptr_t a0 asm ("a0") = arg0;
register uintptr_t a1 asm ("a1") = arg1;
diff --git a/machine/vm.h b/machine/vm.h
index 6d3da4e..29f4535 100644
--- a/machine/vm.h
+++ b/machine/vm.h
@@ -6,11 +6,11 @@
#define MEGAPAGE_SIZE ((uintptr_t)(RISCV_PGSIZE << RISCV_PGLEVEL_BITS))
#if __riscv_xlen == 64
-# define SPTBR_MODE INSERT_FIELD(0, SPTBR64_MODE, SPTBR_MODE_SV39)
+# define SPTBR_MODE_CHOICE INSERT_FIELD(0, SPTBR64_MODE, SPTBR_MODE_SV39)
# define VA_BITS 39
# define GIGAPAGE_SIZE (MEGAPAGE_SIZE << RISCV_PGLEVEL_BITS)
#else
-# define SPTBR_MODE INSERT_FIELD(0, SPTBR32_MODE, SPTBR_MODE_SV32)
+# define SPTBR_MODE_CHOICE INSERT_FIELD(0, SPTBR32_MODE, SPTBR_MODE_SV32)
# define VA_BITS 32
#endif
diff --git a/pk/mmap.c b/pk/mmap.c
index 33c3da2..a063f42 100644
--- a/pk/mmap.c
+++ b/pk/mmap.c
@@ -142,9 +142,9 @@ static uintptr_t __vm_alloc(size_t npage)
static inline pte_t prot_to_type(int prot, int user)
{
pte_t pte = 0;
- if (prot & PROT_READ) pte |= PTE_R;
- if (prot & PROT_WRITE) pte |= PTE_W;
- if (prot & PROT_EXEC) pte |= PTE_X;
+ if (prot & PROT_READ) pte |= PTE_R | PTE_A;
+ if (prot & PROT_WRITE) pte |= PTE_W | PTE_D;
+ if (prot & PROT_EXEC) pte |= PTE_X | PTE_A;
if (pte == 0) pte = PTE_R;
if (user) pte |= PTE_U;
return pte;
@@ -406,6 +406,9 @@ uintptr_t pk_vm_init()
kassert(stack_bottom != (uintptr_t)-1);
current.stack_top = stack_bottom + stack_size;
+ flush_tlb();
+ write_csr(sptbr, ((uintptr_t)root_page_table >> RISCV_PGSHIFT) | SPTBR_MODE_CHOICE);
+
uintptr_t kernel_stack_top = __page_alloc() + RISCV_PGSIZE;
return kernel_stack_top;
}