From 637bf90f93c8101848c67a32be35cce3d79e21c4 Mon Sep 17 00:00:00 2001 From: Quan Nguyen Date: Tue, 21 Jan 2014 15:55:16 -0800 Subject: Move microthread-specific opcodes to opcodes-hwacha-ut --- opcodes-hwacha | 8 -------- opcodes-hwacha-ut | 8 ++++++++ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/opcodes-hwacha b/opcodes-hwacha index d919786..4927f6f 100644 --- a/opcodes-hwacha +++ b/opcodes-hwacha @@ -1,11 +1,3 @@ -# vector scalar instructions -stop 31..25=0 24..20=0 19..15=0 14..12=5 11..7=0 6..2=0x1D 1..0=3 -utidx 31..25=0 24..20=0 19..15=0 14..12=6 rd 6..2=0x1D 1..0=3 -movz 31..25=0 rs2 rs1 14..12=7 rd 6..2=0x1D 1..0=3 -movn 31..25=1 rs2 rs1 14..12=7 rd 6..2=0x1D 1..0=3 -fmovz 31..25=2 rs2 rs1 14..12=7 rd 6..2=0x1D 1..0=3 -fmovn 31..25=3 rs2 rs1 14..12=7 rd 6..2=0x1D 1..0=3 - # rocc format, xd = inst[14], xs1 = inst[13], xs2 = inst[12] # vector instructions diff --git a/opcodes-hwacha-ut b/opcodes-hwacha-ut index ad88fed..eeb6937 100644 --- a/opcodes-hwacha-ut +++ b/opcodes-hwacha-ut @@ -7,6 +7,14 @@ # is one of rd, rs1, rs2, rs3, imm25, imm20, imm12, imm12lo, imm12hi, # shamtw, shamt, rm +# vector scalar instructions +stop 31..25=0 24..20=0 19..15=0 14..12=5 11..7=0 6..2=0x1D 1..0=3 +utidx 31..25=0 24..20=0 19..15=0 14..12=6 rd 6..2=0x1D 1..0=3 +movz 31..25=0 rs2 rs1 14..12=7 rd 6..2=0x1D 1..0=3 +movn 31..25=1 rs2 rs1 14..12=7 rd 6..2=0x1D 1..0=3 +fmovz 31..25=2 rs2 rs1 14..12=7 rd 6..2=0x1D 1..0=3 +fmovn 31..25=3 rs2 rs1 14..12=7 rd 6..2=0x1D 1..0=3 + # half-precision floating-point operations for hwacha microthreads fadd.h rd rs1 rs2 31..27=0x0 rm 26..25=2 6..2=0x14 1..0=3 -- cgit v1.1