From b60b8e3075cb2a995128d06651affb4568dff6eb Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 17:24:00 +0530 Subject: migrate I-extension opcodes - the ordering in these files have changed to preserve the order in the latex- tables - also ecall and ebreak has been moved to rv_i instead of keeping them in 'systems' file. --- opcodes-rv32i | 54 ------------------------------------------------------ opcodes-rv64i | 22 ---------------------- rv32_i | 4 ++++ rv64_i | 17 +++++++++++++++++ rv_i | 39 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 60 insertions(+), 76 deletions(-) delete mode 100644 opcodes-rv32i delete mode 100644 opcodes-rv64i create mode 100644 rv32_i create mode 100644 rv64_i create mode 100644 rv_i diff --git a/opcodes-rv32i b/opcodes-rv32i deleted file mode 100644 index 0d008d8..0000000 --- a/opcodes-rv32i +++ /dev/null @@ -1,54 +0,0 @@ -# format of a line in this file: -# -# -# is given by specifying one or more range/value pairs: -# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) -# -# is one of rd, rs1, rs2, rs3, imm20, imm12, imm12lo, imm12hi, -# shamtw, shamt, rm - -beq bimm12hi rs1 rs2 bimm12lo 14..12=0 6..2=0x18 1..0=3 -bne bimm12hi rs1 rs2 bimm12lo 14..12=1 6..2=0x18 1..0=3 -blt bimm12hi rs1 rs2 bimm12lo 14..12=4 6..2=0x18 1..0=3 -bge bimm12hi rs1 rs2 bimm12lo 14..12=5 6..2=0x18 1..0=3 -bltu bimm12hi rs1 rs2 bimm12lo 14..12=6 6..2=0x18 1..0=3 -bgeu bimm12hi rs1 rs2 bimm12lo 14..12=7 6..2=0x18 1..0=3 - -jalr rd rs1 imm12 14..12=0 6..2=0x19 1..0=3 - -jal rd jimm20 6..2=0x1b 1..0=3 - -lui rd imm20 6..2=0x0D 1..0=3 -auipc rd imm20 6..2=0x05 1..0=3 - -addi rd rs1 imm12 14..12=0 6..2=0x04 1..0=3 -slti rd rs1 imm12 14..12=2 6..2=0x04 1..0=3 -sltiu rd rs1 imm12 14..12=3 6..2=0x04 1..0=3 -xori rd rs1 imm12 14..12=4 6..2=0x04 1..0=3 -ori rd rs1 imm12 14..12=6 6..2=0x04 1..0=3 -andi rd rs1 imm12 14..12=7 6..2=0x04 1..0=3 - -add rd rs1 rs2 31..25=0 14..12=0 6..2=0x0C 1..0=3 -sub rd rs1 rs2 31..25=32 14..12=0 6..2=0x0C 1..0=3 -sll rd rs1 rs2 31..25=0 14..12=1 6..2=0x0C 1..0=3 -slt rd rs1 rs2 31..25=0 14..12=2 6..2=0x0C 1..0=3 -sltu rd rs1 rs2 31..25=0 14..12=3 6..2=0x0C 1..0=3 -xor rd rs1 rs2 31..25=0 14..12=4 6..2=0x0C 1..0=3 -srl rd rs1 rs2 31..25=0 14..12=5 6..2=0x0C 1..0=3 -sra rd rs1 rs2 31..25=32 14..12=5 6..2=0x0C 1..0=3 -or rd rs1 rs2 31..25=0 14..12=6 6..2=0x0C 1..0=3 -and rd rs1 rs2 31..25=0 14..12=7 6..2=0x0C 1..0=3 - -lb rd rs1 imm12 14..12=0 6..2=0x00 1..0=3 -lh rd rs1 imm12 14..12=1 6..2=0x00 1..0=3 -lw rd rs1 imm12 14..12=2 6..2=0x00 1..0=3 -lbu rd rs1 imm12 14..12=4 6..2=0x00 1..0=3 -lhu rd rs1 imm12 14..12=5 6..2=0x00 1..0=3 - -sb imm12hi rs1 rs2 imm12lo 14..12=0 6..2=0x08 1..0=3 -sh imm12hi rs1 rs2 imm12lo 14..12=1 6..2=0x08 1..0=3 -sw imm12hi rs1 rs2 imm12lo 14..12=2 6..2=0x08 1..0=3 - -fence fm pred succ rs1 14..12=0 rd 6..2=0x03 1..0=3 -fence.i imm12 rs1 14..12=1 rd 6..2=0x03 1..0=3 - diff --git a/opcodes-rv64i b/opcodes-rv64i deleted file mode 100644 index adced5b..0000000 --- a/opcodes-rv64i +++ /dev/null @@ -1,22 +0,0 @@ -# RV64I additions to RV32I - -addiw rd rs1 imm12 14..12=0 6..2=0x06 1..0=3 -slliw rd rs1 31..25=0 shamtw 14..12=1 6..2=0x06 1..0=3 -srliw rd rs1 31..25=0 shamtw 14..12=5 6..2=0x06 1..0=3 -sraiw rd rs1 31..25=32 shamtw 14..12=5 6..2=0x06 1..0=3 - -addw rd rs1 rs2 31..25=0 14..12=0 6..2=0x0E 1..0=3 -subw rd rs1 rs2 31..25=32 14..12=0 6..2=0x0E 1..0=3 -sllw rd rs1 rs2 31..25=0 14..12=1 6..2=0x0E 1..0=3 -srlw rd rs1 rs2 31..25=0 14..12=5 6..2=0x0E 1..0=3 -sraw rd rs1 rs2 31..25=32 14..12=5 6..2=0x0E 1..0=3 - -ld rd rs1 imm12 14..12=3 6..2=0x00 1..0=3 -lwu rd rs1 imm12 14..12=6 6..2=0x00 1..0=3 - -sd imm12hi rs1 rs2 imm12lo 14..12=3 6..2=0x08 1..0=3 - -# RV32 versions of these are in opcodes-pseudo -slli rd rs1 31..26=0 shamt 14..12=1 6..2=0x04 1..0=3 -srli rd rs1 31..26=0 shamt 14..12=5 6..2=0x04 1..0=3 -srai rd rs1 31..26=16 shamt 14..12=5 6..2=0x04 1..0=3 diff --git a/rv32_i b/rv32_i new file mode 100644 index 0000000..28d371a --- /dev/null +++ b/rv32_i @@ -0,0 +1,4 @@ +$pseudo_op rv64_i::slli slli rd rs1 shamtw 31..25=0 14..12=1 6..2=0x04 1..0=3 +$pseudo_op rv64_i::srli srli rd rs1 shamtw 31..25=0 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_i::srai srai rd rs1 shamtw 31..25=32 14..12=5 6..2=0x04 1..0=3 + diff --git a/rv64_i b/rv64_i new file mode 100644 index 0000000..1d88e59 --- /dev/null +++ b/rv64_i @@ -0,0 +1,17 @@ +# RV64I additions to RV32I + +lwu rd rs1 imm12 14..12=6 6..2=0x00 1..0=3 +ld rd rs1 imm12 14..12=3 6..2=0x00 1..0=3 +sd imm12hi rs1 rs2 imm12lo 14..12=3 6..2=0x08 1..0=3 +slli rd rs1 31..26=0 shamt 14..12=1 6..2=0x04 1..0=3 +srli rd rs1 31..26=0 shamt 14..12=5 6..2=0x04 1..0=3 +srai rd rs1 31..26=16 shamt 14..12=5 6..2=0x04 1..0=3 +addiw rd rs1 imm12 14..12=0 6..2=0x06 1..0=3 +slliw rd rs1 31..25=0 shamtw 14..12=1 6..2=0x06 1..0=3 +srliw rd rs1 31..25=0 shamtw 14..12=5 6..2=0x06 1..0=3 +sraiw rd rs1 31..25=32 shamtw 14..12=5 6..2=0x06 1..0=3 +addw rd rs1 rs2 31..25=0 14..12=0 6..2=0x0E 1..0=3 +subw rd rs1 rs2 31..25=32 14..12=0 6..2=0x0E 1..0=3 +sllw rd rs1 rs2 31..25=0 14..12=1 6..2=0x0E 1..0=3 +srlw rd rs1 rs2 31..25=0 14..12=5 6..2=0x0E 1..0=3 +sraw rd rs1 rs2 31..25=32 14..12=5 6..2=0x0E 1..0=3 diff --git a/rv_i b/rv_i new file mode 100644 index 0000000..8b1569a --- /dev/null +++ b/rv_i @@ -0,0 +1,39 @@ +# rv_i + +lui rd imm20 6..2=0x0D 1..0=3 +auipc rd imm20 6..2=0x05 1..0=3 +jal rd jimm20 6..2=0x1b 1..0=3 +jalr rd rs1 imm12 14..12=0 6..2=0x19 1..0=3 +beq bimm12hi rs1 rs2 bimm12lo 14..12=0 6..2=0x18 1..0=3 +bne bimm12hi rs1 rs2 bimm12lo 14..12=1 6..2=0x18 1..0=3 +blt bimm12hi rs1 rs2 bimm12lo 14..12=4 6..2=0x18 1..0=3 +bge bimm12hi rs1 rs2 bimm12lo 14..12=5 6..2=0x18 1..0=3 +bltu bimm12hi rs1 rs2 bimm12lo 14..12=6 6..2=0x18 1..0=3 +bgeu bimm12hi rs1 rs2 bimm12lo 14..12=7 6..2=0x18 1..0=3 +lb rd rs1 imm12 14..12=0 6..2=0x00 1..0=3 +lh rd rs1 imm12 14..12=1 6..2=0x00 1..0=3 +lw rd rs1 imm12 14..12=2 6..2=0x00 1..0=3 +lbu rd rs1 imm12 14..12=4 6..2=0x00 1..0=3 +lhu rd rs1 imm12 14..12=5 6..2=0x00 1..0=3 +sb imm12hi rs1 rs2 imm12lo 14..12=0 6..2=0x08 1..0=3 +sh imm12hi rs1 rs2 imm12lo 14..12=1 6..2=0x08 1..0=3 +sw imm12hi rs1 rs2 imm12lo 14..12=2 6..2=0x08 1..0=3 +addi rd rs1 imm12 14..12=0 6..2=0x04 1..0=3 +slti rd rs1 imm12 14..12=2 6..2=0x04 1..0=3 +sltiu rd rs1 imm12 14..12=3 6..2=0x04 1..0=3 +xori rd rs1 imm12 14..12=4 6..2=0x04 1..0=3 +ori rd rs1 imm12 14..12=6 6..2=0x04 1..0=3 +andi rd rs1 imm12 14..12=7 6..2=0x04 1..0=3 +add rd rs1 rs2 31..25=0 14..12=0 6..2=0x0C 1..0=3 +sub rd rs1 rs2 31..25=32 14..12=0 6..2=0x0C 1..0=3 +sll rd rs1 rs2 31..25=0 14..12=1 6..2=0x0C 1..0=3 +slt rd rs1 rs2 31..25=0 14..12=2 6..2=0x0C 1..0=3 +sltu rd rs1 rs2 31..25=0 14..12=3 6..2=0x0C 1..0=3 +xor rd rs1 rs2 31..25=0 14..12=4 6..2=0x0C 1..0=3 +srl rd rs1 rs2 31..25=0 14..12=5 6..2=0x0C 1..0=3 +sra rd rs1 rs2 31..25=32 14..12=5 6..2=0x0C 1..0=3 +or rd rs1 rs2 31..25=0 14..12=6 6..2=0x0C 1..0=3 +and rd rs1 rs2 31..25=0 14..12=7 6..2=0x0C 1..0=3 +fence fm pred succ rs1 14..12=0 rd 6..2=0x03 1..0=3 +ecall 31..20=0x000 19..7=0 6..2=0x1C 1..0=3 +ebreak 31..20=0x001 19..7=0 6..2=0x1C 1..0=3 -- cgit v1.1 From c07042cb6b66076ff7935fa79a59ae451b0f866a Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 17:26:08 +0530 Subject: migrate M-extension opcodes - the files are simply renamed --- opcodes-rv32m | 8 -------- opcodes-rv64m | 7 ------- rv64_m | 6 ++++++ rv_m | 8 ++++++++ 4 files changed, 14 insertions(+), 15 deletions(-) delete mode 100644 opcodes-rv32m delete mode 100644 opcodes-rv64m create mode 100644 rv64_m create mode 100644 rv_m diff --git a/opcodes-rv32m b/opcodes-rv32m deleted file mode 100644 index 51e6786..0000000 --- a/opcodes-rv32m +++ /dev/null @@ -1,8 +0,0 @@ -mul rd rs1 rs2 31..25=1 14..12=0 6..2=0x0C 1..0=3 -mulh rd rs1 rs2 31..25=1 14..12=1 6..2=0x0C 1..0=3 -mulhsu rd rs1 rs2 31..25=1 14..12=2 6..2=0x0C 1..0=3 -mulhu rd rs1 rs2 31..25=1 14..12=3 6..2=0x0C 1..0=3 -div rd rs1 rs2 31..25=1 14..12=4 6..2=0x0C 1..0=3 -divu rd rs1 rs2 31..25=1 14..12=5 6..2=0x0C 1..0=3 -rem rd rs1 rs2 31..25=1 14..12=6 6..2=0x0C 1..0=3 -remu rd rs1 rs2 31..25=1 14..12=7 6..2=0x0C 1..0=3 diff --git a/opcodes-rv64m b/opcodes-rv64m deleted file mode 100644 index 939c00c..0000000 --- a/opcodes-rv64m +++ /dev/null @@ -1,7 +0,0 @@ -# RV64M additions to RV32M - -mulw rd rs1 rs2 31..25=1 14..12=0 6..2=0x0E 1..0=3 -divw rd rs1 rs2 31..25=1 14..12=4 6..2=0x0E 1..0=3 -divuw rd rs1 rs2 31..25=1 14..12=5 6..2=0x0E 1..0=3 -remw rd rs1 rs2 31..25=1 14..12=6 6..2=0x0E 1..0=3 -remuw rd rs1 rs2 31..25=1 14..12=7 6..2=0x0E 1..0=3 diff --git a/rv64_m b/rv64_m new file mode 100644 index 0000000..cfac0b1 --- /dev/null +++ b/rv64_m @@ -0,0 +1,6 @@ +# RV64M additions to RV32M +mulw rd rs1 rs2 31..25=1 14..12=0 6..2=0x0E 1..0=3 +divw rd rs1 rs2 31..25=1 14..12=4 6..2=0x0E 1..0=3 +divuw rd rs1 rs2 31..25=1 14..12=5 6..2=0x0E 1..0=3 +remw rd rs1 rs2 31..25=1 14..12=6 6..2=0x0E 1..0=3 +remuw rd rs1 rs2 31..25=1 14..12=7 6..2=0x0E 1..0=3 diff --git a/rv_m b/rv_m new file mode 100644 index 0000000..51e6786 --- /dev/null +++ b/rv_m @@ -0,0 +1,8 @@ +mul rd rs1 rs2 31..25=1 14..12=0 6..2=0x0C 1..0=3 +mulh rd rs1 rs2 31..25=1 14..12=1 6..2=0x0C 1..0=3 +mulhsu rd rs1 rs2 31..25=1 14..12=2 6..2=0x0C 1..0=3 +mulhu rd rs1 rs2 31..25=1 14..12=3 6..2=0x0C 1..0=3 +div rd rs1 rs2 31..25=1 14..12=4 6..2=0x0C 1..0=3 +divu rd rs1 rs2 31..25=1 14..12=5 6..2=0x0C 1..0=3 +rem rd rs1 rs2 31..25=1 14..12=6 6..2=0x0C 1..0=3 +remu rd rs1 rs2 31..25=1 14..12=7 6..2=0x0C 1..0=3 -- cgit v1.1 From c7192318d98c2f83000022f8065cac648759f075 Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 17:28:26 +0530 Subject: migrate A-extension opcodes - the re-ordering of opcodes s necessary to preserve latex-table order --- opcodes-rv32a | 11 ----------- opcodes-rv64a | 13 ------------- rv64_a | 12 ++++++++++++ rv_a | 11 +++++++++++ 4 files changed, 23 insertions(+), 24 deletions(-) delete mode 100644 opcodes-rv32a delete mode 100644 opcodes-rv64a create mode 100644 rv64_a create mode 100644 rv_a diff --git a/opcodes-rv32a b/opcodes-rv32a deleted file mode 100644 index f194b7c..0000000 --- a/opcodes-rv32a +++ /dev/null @@ -1,11 +0,0 @@ -amoadd.w rd rs1 rs2 aqrl 31..29=0 28..27=0 14..12=2 6..2=0x0B 1..0=3 -amoxor.w rd rs1 rs2 aqrl 31..29=1 28..27=0 14..12=2 6..2=0x0B 1..0=3 -amoor.w rd rs1 rs2 aqrl 31..29=2 28..27=0 14..12=2 6..2=0x0B 1..0=3 -amoand.w rd rs1 rs2 aqrl 31..29=3 28..27=0 14..12=2 6..2=0x0B 1..0=3 -amomin.w rd rs1 rs2 aqrl 31..29=4 28..27=0 14..12=2 6..2=0x0B 1..0=3 -amomax.w rd rs1 rs2 aqrl 31..29=5 28..27=0 14..12=2 6..2=0x0B 1..0=3 -amominu.w rd rs1 rs2 aqrl 31..29=6 28..27=0 14..12=2 6..2=0x0B 1..0=3 -amomaxu.w rd rs1 rs2 aqrl 31..29=7 28..27=0 14..12=2 6..2=0x0B 1..0=3 -amoswap.w rd rs1 rs2 aqrl 31..29=0 28..27=1 14..12=2 6..2=0x0B 1..0=3 -lr.w rd rs1 24..20=0 aqrl 31..29=0 28..27=2 14..12=2 6..2=0x0B 1..0=3 -sc.w rd rs1 rs2 aqrl 31..29=0 28..27=3 14..12=2 6..2=0x0B 1..0=3 diff --git a/opcodes-rv64a b/opcodes-rv64a deleted file mode 100644 index 23fb7aa..0000000 --- a/opcodes-rv64a +++ /dev/null @@ -1,13 +0,0 @@ -# RV64A additions to RV32A - -amoadd.d rd rs1 rs2 aqrl 31..29=0 28..27=0 14..12=3 6..2=0x0B 1..0=3 -amoxor.d rd rs1 rs2 aqrl 31..29=1 28..27=0 14..12=3 6..2=0x0B 1..0=3 -amoor.d rd rs1 rs2 aqrl 31..29=2 28..27=0 14..12=3 6..2=0x0B 1..0=3 -amoand.d rd rs1 rs2 aqrl 31..29=3 28..27=0 14..12=3 6..2=0x0B 1..0=3 -amomin.d rd rs1 rs2 aqrl 31..29=4 28..27=0 14..12=3 6..2=0x0B 1..0=3 -amomax.d rd rs1 rs2 aqrl 31..29=5 28..27=0 14..12=3 6..2=0x0B 1..0=3 -amominu.d rd rs1 rs2 aqrl 31..29=6 28..27=0 14..12=3 6..2=0x0B 1..0=3 -amomaxu.d rd rs1 rs2 aqrl 31..29=7 28..27=0 14..12=3 6..2=0x0B 1..0=3 -amoswap.d rd rs1 rs2 aqrl 31..29=0 28..27=1 14..12=3 6..2=0x0B 1..0=3 -lr.d rd rs1 24..20=0 aqrl 31..29=0 28..27=2 14..12=3 6..2=0x0B 1..0=3 -sc.d rd rs1 rs2 aqrl 31..29=0 28..27=3 14..12=3 6..2=0x0B 1..0=3 diff --git a/rv64_a b/rv64_a new file mode 100644 index 0000000..fe208e9 --- /dev/null +++ b/rv64_a @@ -0,0 +1,12 @@ +# RV64A additions to RV32A +lr.d rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=3 6..2=0x0B 1..0=3 +sc.d rd rs1 rs2 aq rl 31..29=0 28..27=3 14..12=3 6..2=0x0B 1..0=3 +amoswap.d rd rs1 rs2 aq rl 31..29=0 28..27=1 14..12=3 6..2=0x0B 1..0=3 +amoadd.d rd rs1 rs2 aq rl 31..29=0 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amoxor.d rd rs1 rs2 aq rl 31..29=1 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amoand.d rd rs1 rs2 aq rl 31..29=3 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amoor.d rd rs1 rs2 aq rl 31..29=2 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amomin.d rd rs1 rs2 aq rl 31..29=4 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amomax.d rd rs1 rs2 aq rl 31..29=5 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amominu.d rd rs1 rs2 aq rl 31..29=6 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amomaxu.d rd rs1 rs2 aq rl 31..29=7 28..27=0 14..12=3 6..2=0x0B 1..0=3 diff --git a/rv_a b/rv_a new file mode 100644 index 0000000..1a70e40 --- /dev/null +++ b/rv_a @@ -0,0 +1,11 @@ +lr.w rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=2 6..2=0x0B 1..0=3 +sc.w rd rs1 rs2 aq rl 31..29=0 28..27=3 14..12=2 6..2=0x0B 1..0=3 +amoswap.w rd rs1 rs2 aq rl 31..29=0 28..27=1 14..12=2 6..2=0x0B 1..0=3 +amoadd.w rd rs1 rs2 aq rl 31..29=0 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amoxor.w rd rs1 rs2 aq rl 31..29=1 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amoand.w rd rs1 rs2 aq rl 31..29=3 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amoor.w rd rs1 rs2 aq rl 31..29=2 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amomin.w rd rs1 rs2 aq rl 31..29=4 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amomax.w rd rs1 rs2 aq rl 31..29=5 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amominu.w rd rs1 rs2 aq rl 31..29=6 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amomaxu.w rd rs1 rs2 aq rl 31..29=7 28..27=0 14..12=2 6..2=0x0B 1..0=3 -- cgit v1.1 From 34edfce7afebfb95f2eab017b939a5ab912696ca Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 17:30:06 +0530 Subject: migrate F-extension opcodes - all changes involve re-ordering to preserve order in latex-tables --- opcodes-rv32f | 32 -------------------------------- opcodes-rv64f | 7 ------- rv64_f | 7 +++++++ rv_f | 26 ++++++++++++++++++++++++++ 4 files changed, 33 insertions(+), 39 deletions(-) delete mode 100644 opcodes-rv32f delete mode 100644 opcodes-rv64f create mode 100644 rv64_f create mode 100644 rv_f diff --git a/opcodes-rv32f b/opcodes-rv32f deleted file mode 100644 index 6f6e840..0000000 --- a/opcodes-rv32f +++ /dev/null @@ -1,32 +0,0 @@ -fadd.s rd rs1 rs2 31..27=0x00 rm 26..25=0 6..2=0x14 1..0=3 -fsub.s rd rs1 rs2 31..27=0x01 rm 26..25=0 6..2=0x14 1..0=3 -fmul.s rd rs1 rs2 31..27=0x02 rm 26..25=0 6..2=0x14 1..0=3 -fdiv.s rd rs1 rs2 31..27=0x03 rm 26..25=0 6..2=0x14 1..0=3 -fsgnj.s rd rs1 rs2 31..27=0x04 14..12=0 26..25=0 6..2=0x14 1..0=3 -fsgnjn.s rd rs1 rs2 31..27=0x04 14..12=1 26..25=0 6..2=0x14 1..0=3 -fsgnjx.s rd rs1 rs2 31..27=0x04 14..12=2 26..25=0 6..2=0x14 1..0=3 -fmin.s rd rs1 rs2 31..27=0x05 14..12=0 26..25=0 6..2=0x14 1..0=3 -fmax.s rd rs1 rs2 31..27=0x05 14..12=1 26..25=0 6..2=0x14 1..0=3 -fsqrt.s rd rs1 24..20=0 31..27=0x0B rm 26..25=0 6..2=0x14 1..0=3 - -fle.s rd rs1 rs2 31..27=0x14 14..12=0 26..25=0 6..2=0x14 1..0=3 -flt.s rd rs1 rs2 31..27=0x14 14..12=1 26..25=0 6..2=0x14 1..0=3 -feq.s rd rs1 rs2 31..27=0x14 14..12=2 26..25=0 6..2=0x14 1..0=3 - -fcvt.w.s rd rs1 24..20=0 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 -fcvt.wu.s rd rs1 24..20=1 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 -fmv.x.w rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3 -fclass.s rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=0 6..2=0x14 1..0=3 - -fcvt.s.w rd rs1 24..20=0 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 -fcvt.s.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 -fmv.w.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 - -flw rd rs1 imm12 14..12=2 6..2=0x01 1..0=3 - -fsw imm12hi rs1 rs2 imm12lo 14..12=2 6..2=0x09 1..0=3 - -fmadd.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x10 1..0=3 -fmsub.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x11 1..0=3 -fnmsub.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x12 1..0=3 -fnmadd.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x13 1..0=3 diff --git a/opcodes-rv64f b/opcodes-rv64f deleted file mode 100644 index 22a9a01..0000000 --- a/opcodes-rv64f +++ /dev/null @@ -1,7 +0,0 @@ -# RV64F additions to RV32F - -fcvt.l.s rd rs1 24..20=2 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 -fcvt.lu.s rd rs1 24..20=3 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 - -fcvt.s.l rd rs1 24..20=2 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 -fcvt.s.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 diff --git a/rv64_f b/rv64_f new file mode 100644 index 0000000..787677c --- /dev/null +++ b/rv64_f @@ -0,0 +1,7 @@ +# RV64F additions to RV32F + +fcvt.l.s rd rs1 24..20=2 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.lu.s rd rs1 24..20=3 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.s.l rd rs1 24..20=2 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 +fcvt.s.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 + diff --git a/rv_f b/rv_f new file mode 100644 index 0000000..c148dd2 --- /dev/null +++ b/rv_f @@ -0,0 +1,26 @@ +flw rd rs1 imm12 14..12=2 6..2=0x01 1..0=3 +fsw imm12hi rs1 rs2 imm12lo 14..12=2 6..2=0x09 1..0=3 +fmadd.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x10 1..0=3 +fmsub.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x11 1..0=3 +fnmsub.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x12 1..0=3 +fnmadd.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x13 1..0=3 +fadd.s rd rs1 rs2 31..27=0x00 rm 26..25=0 6..2=0x14 1..0=3 +fsub.s rd rs1 rs2 31..27=0x01 rm 26..25=0 6..2=0x14 1..0=3 +fmul.s rd rs1 rs2 31..27=0x02 rm 26..25=0 6..2=0x14 1..0=3 +fdiv.s rd rs1 rs2 31..27=0x03 rm 26..25=0 6..2=0x14 1..0=3 +fsqrt.s rd rs1 24..20=0 31..27=0x0B rm 26..25=0 6..2=0x14 1..0=3 +fsgnj.s rd rs1 rs2 31..27=0x04 14..12=0 26..25=0 6..2=0x14 1..0=3 +fsgnjn.s rd rs1 rs2 31..27=0x04 14..12=1 26..25=0 6..2=0x14 1..0=3 +fsgnjx.s rd rs1 rs2 31..27=0x04 14..12=2 26..25=0 6..2=0x14 1..0=3 +fmin.s rd rs1 rs2 31..27=0x05 14..12=0 26..25=0 6..2=0x14 1..0=3 +fmax.s rd rs1 rs2 31..27=0x05 14..12=1 26..25=0 6..2=0x14 1..0=3 +fcvt.w.s rd rs1 24..20=0 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.wu.s rd rs1 24..20=1 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 +fmv.x.w rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3 +feq.s rd rs1 rs2 31..27=0x14 14..12=2 26..25=0 6..2=0x14 1..0=3 +flt.s rd rs1 rs2 31..27=0x14 14..12=1 26..25=0 6..2=0x14 1..0=3 +fle.s rd rs1 rs2 31..27=0x14 14..12=0 26..25=0 6..2=0x14 1..0=3 +fclass.s rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=0 6..2=0x14 1..0=3 +fcvt.s.w rd rs1 24..20=0 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 +fcvt.s.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 +fmv.w.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 -- cgit v1.1 From 56147c766f68cf19f826fde0e4897e988d658bcf Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 17:30:26 +0530 Subject: migratte D-extension opcodes - all changes involve re-ordering to preserve order in latex-tables --- opcodes-rv32d | 32 -------------------------------- opcodes-rv64d | 9 --------- rv64_d | 7 +++++++ rv_d | 26 ++++++++++++++++++++++++++ 4 files changed, 33 insertions(+), 41 deletions(-) delete mode 100644 opcodes-rv32d delete mode 100644 opcodes-rv64d create mode 100644 rv64_d create mode 100644 rv_d diff --git a/opcodes-rv32d b/opcodes-rv32d deleted file mode 100644 index 16d7ae5..0000000 --- a/opcodes-rv32d +++ /dev/null @@ -1,32 +0,0 @@ -fadd.d rd rs1 rs2 31..27=0x00 rm 26..25=1 6..2=0x14 1..0=3 -fsub.d rd rs1 rs2 31..27=0x01 rm 26..25=1 6..2=0x14 1..0=3 -fmul.d rd rs1 rs2 31..27=0x02 rm 26..25=1 6..2=0x14 1..0=3 -fdiv.d rd rs1 rs2 31..27=0x03 rm 26..25=1 6..2=0x14 1..0=3 -fsgnj.d rd rs1 rs2 31..27=0x04 14..12=0 26..25=1 6..2=0x14 1..0=3 -fsgnjn.d rd rs1 rs2 31..27=0x04 14..12=1 26..25=1 6..2=0x14 1..0=3 -fsgnjx.d rd rs1 rs2 31..27=0x04 14..12=2 26..25=1 6..2=0x14 1..0=3 -fmin.d rd rs1 rs2 31..27=0x05 14..12=0 26..25=1 6..2=0x14 1..0=3 -fmax.d rd rs1 rs2 31..27=0x05 14..12=1 26..25=1 6..2=0x14 1..0=3 -fcvt.s.d rd rs1 24..20=1 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 -fcvt.d.s rd rs1 24..20=0 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 -fsqrt.d rd rs1 24..20=0 31..27=0x0B rm 26..25=1 6..2=0x14 1..0=3 - -fle.d rd rs1 rs2 31..27=0x14 14..12=0 26..25=1 6..2=0x14 1..0=3 -flt.d rd rs1 rs2 31..27=0x14 14..12=1 26..25=1 6..2=0x14 1..0=3 -feq.d rd rs1 rs2 31..27=0x14 14..12=2 26..25=1 6..2=0x14 1..0=3 - -fcvt.w.d rd rs1 24..20=0 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 -fcvt.wu.d rd rs1 24..20=1 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 -fclass.d rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=1 6..2=0x14 1..0=3 - -fcvt.d.w rd rs1 24..20=0 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 -fcvt.d.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 - -fld rd rs1 imm12 14..12=3 6..2=0x01 1..0=3 - -fsd imm12hi rs1 rs2 imm12lo 14..12=3 6..2=0x09 1..0=3 - -fmadd.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x10 1..0=3 -fmsub.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x11 1..0=3 -fnmsub.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x12 1..0=3 -fnmadd.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x13 1..0=3 diff --git a/opcodes-rv64d b/opcodes-rv64d deleted file mode 100644 index c54d865..0000000 --- a/opcodes-rv64d +++ /dev/null @@ -1,9 +0,0 @@ -# RV64D additions to RV32D - -fcvt.l.d rd rs1 24..20=2 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 -fcvt.lu.d rd rs1 24..20=3 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 -fmv.x.d rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=1 6..2=0x14 1..0=3 - -fcvt.d.l rd rs1 24..20=2 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 -fcvt.d.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 -fmv.d.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=1 6..2=0x14 1..0=3 diff --git a/rv64_d b/rv64_d new file mode 100644 index 0000000..d8c8299 --- /dev/null +++ b/rv64_d @@ -0,0 +1,7 @@ +# RV64D additions to RV32D +fcvt.l.d rd rs1 24..20=2 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 +fcvt.lu.d rd rs1 24..20=3 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 +fmv.x.d rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=1 6..2=0x14 1..0=3 +fcvt.d.l rd rs1 24..20=2 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 +fcvt.d.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 +fmv.d.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=1 6..2=0x14 1..0=3 diff --git a/rv_d b/rv_d new file mode 100644 index 0000000..8c3a3d3 --- /dev/null +++ b/rv_d @@ -0,0 +1,26 @@ +fld rd rs1 imm12 14..12=3 6..2=0x01 1..0=3 +fsd imm12hi rs1 rs2 imm12lo 14..12=3 6..2=0x09 1..0=3 +fmadd.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x10 1..0=3 +fmsub.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x11 1..0=3 +fnmsub.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x12 1..0=3 +fnmadd.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x13 1..0=3 +fadd.d rd rs1 rs2 31..27=0x00 rm 26..25=1 6..2=0x14 1..0=3 +fsub.d rd rs1 rs2 31..27=0x01 rm 26..25=1 6..2=0x14 1..0=3 +fmul.d rd rs1 rs2 31..27=0x02 rm 26..25=1 6..2=0x14 1..0=3 +fdiv.d rd rs1 rs2 31..27=0x03 rm 26..25=1 6..2=0x14 1..0=3 +fsqrt.d rd rs1 24..20=0 31..27=0x0B rm 26..25=1 6..2=0x14 1..0=3 +fsgnj.d rd rs1 rs2 31..27=0x04 14..12=0 26..25=1 6..2=0x14 1..0=3 +fsgnjn.d rd rs1 rs2 31..27=0x04 14..12=1 26..25=1 6..2=0x14 1..0=3 +fsgnjx.d rd rs1 rs2 31..27=0x04 14..12=2 26..25=1 6..2=0x14 1..0=3 +fmin.d rd rs1 rs2 31..27=0x05 14..12=0 26..25=1 6..2=0x14 1..0=3 +fmax.d rd rs1 rs2 31..27=0x05 14..12=1 26..25=1 6..2=0x14 1..0=3 +fcvt.s.d rd rs1 24..20=1 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.d.s rd rs1 24..20=0 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 +feq.d rd rs1 rs2 31..27=0x14 14..12=2 26..25=1 6..2=0x14 1..0=3 +flt.d rd rs1 rs2 31..27=0x14 14..12=1 26..25=1 6..2=0x14 1..0=3 +fle.d rd rs1 rs2 31..27=0x14 14..12=0 26..25=1 6..2=0x14 1..0=3 +fclass.d rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=1 6..2=0x14 1..0=3 +fcvt.w.d rd rs1 24..20=0 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 +fcvt.wu.d rd rs1 24..20=1 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 +fcvt.d.w rd rs1 24..20=0 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 +fcvt.d.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 -- cgit v1.1 From 88085a5f6bbb74cb434ff62bacc5912f41fb913b Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 17:38:10 +0530 Subject: migrate C-extension opcodes (major) - the previous opcodes used ignore to define immediate fields instead of assigning arg names to it. This is made it difficult to parse and decode the instructions. - this commit assigns unique names to immediate fields in accordance to what has been done elsewhere. Note these names hold no correspondence to the spec and are defined here purely to ease decoding - This commit also splits the instructions which depend on F/D/Q in to their respective files as per new naming convention - c.nop encoding has been changed to include hints as well. --- opcodes-rv32c | 5 ----- opcodes-rv64c | 14 -------------- opcodes-rvc | 46 ---------------------------------------------- rv128_c | 15 +++++++++++++++ rv32_c | 5 +++++ rv32_c_f | 8 ++++++++ rv64_c | 17 +++++++++++++++++ rv_c | 32 ++++++++++++++++++++++++++++++++ rv_c_d | 8 ++++++++ 9 files changed, 85 insertions(+), 65 deletions(-) delete mode 100644 opcodes-rv32c delete mode 100644 opcodes-rv64c delete mode 100644 opcodes-rvc create mode 100644 rv128_c create mode 100644 rv32_c create mode 100644 rv32_c_f create mode 100644 rv64_c create mode 100644 rv_c create mode 100644 rv_c_d diff --git a/opcodes-rv32c b/opcodes-rv32c deleted file mode 100644 index d91f288..0000000 --- a/opcodes-rv32c +++ /dev/null @@ -1,5 +0,0 @@ -# RV32C additions to RVC - -@c.srli.rv32 1..0=1 15..13=4 12=0 11..10=0 9..2=ignore -@c.srai.rv32 1..0=1 15..13=4 12=0 11..10=1 9..2=ignore -@c.slli.rv32 1..0=2 15..13=0 12=0 11..2=ignore diff --git a/opcodes-rv64c b/opcodes-rv64c deleted file mode 100644 index 7efc7c5..0000000 --- a/opcodes-rv64c +++ /dev/null @@ -1,14 +0,0 @@ -# RV64C additions to RVC - -# C0 encoding space -@c.ld 1..0=0 15..13=3 12=ignore 11..2=ignore # c.flw for RV32 -@c.sd 1..0=0 15..13=7 12=ignore 11..2=ignore # c.fsw for RV32 - -# C1 encoding space -c.subw 1..0=1 15..13=4 12=1 11..10=3 9..7=ignore 6..5=0 4..2=ignore -c.addw 1..0=1 15..13=4 12=1 11..10=3 9..7=ignore 6..5=1 4..2=ignore -@c.addiw 1..0=1 15..13=1 12=ignore 11..2=ignore # c.jal for RV32 - -# C2 encoding space -@c.ldsp 1..0=2 15..13=3 12=ignore 11..2=ignore # c.flwsp for RV32 -@c.sdsp 1..0=2 15..13=7 12=ignore 11..2=ignore # c.fswsp for RV32 diff --git a/opcodes-rvc b/opcodes-rvc deleted file mode 100644 index 64fc19a..0000000 --- a/opcodes-rvc +++ /dev/null @@ -1,46 +0,0 @@ -# compressed instructions - -# these aren't really pseudo-ops, but they overlay other encodings, -# so they are here to prevent parse_opcodes from barfing - -@c.nop 1..0=1 15..13=0 12=0 11..7=0 6..2=0 -@c.addi16sp 1..0=1 15..13=3 12=ignore 11..7=2 6..2=ignore -@c.jr 1..0=2 15..13=4 12=0 11..7=ignore 6..2=0 -@c.jalr 1..0=2 15..13=4 12=1 11..7=ignore 6..2=0 -@c.ebreak 1..0=2 15..13=4 12=1 11..7=0 6..2=0 - -# C0 encoding space -c.addi4spn 1..0=0 15..13=0 12=ignore 11..2=ignore -c.fld 1..0=0 15..13=1 12=ignore 11..2=ignore # c.lq for RV128 -c.lw 1..0=0 15..13=2 12=ignore 11..2=ignore -c.flw 1..0=0 15..13=3 12=ignore 11..2=ignore # c.ld for RV64 -c.fsd 1..0=0 15..13=5 12=ignore 11..2=ignore # c.sq for RV128 -c.sw 1..0=0 15..13=6 12=ignore 11..2=ignore -c.fsw 1..0=0 15..13=7 12=ignore 11..2=ignore # c.sd for RV64 - -# C1 encoding space -c.addi 1..0=1 15..13=0 12=ignore 11..2=ignore -c.jal 1..0=1 15..13=1 12=ignore 11..2=ignore # c.addiw for RV64 -c.li 1..0=1 15..13=2 12=ignore 11..2=ignore -c.lui 1..0=1 15..13=3 12=ignore 11..2=ignore # c.addi16sp when rd=2 -c.srli 1..0=1 15..13=4 12=ignore 11..10=0 9..2=ignore -c.srai 1..0=1 15..13=4 12=ignore 11..10=1 9..2=ignore -c.andi 1..0=1 15..13=4 12=ignore 11..10=2 9..2=ignore -c.sub 1..0=1 15..13=4 12=0 11..10=3 9..7=ignore 6..5=0 4..2=ignore -c.xor 1..0=1 15..13=4 12=0 11..10=3 9..7=ignore 6..5=1 4..2=ignore -c.or 1..0=1 15..13=4 12=0 11..10=3 9..7=ignore 6..5=2 4..2=ignore -c.and 1..0=1 15..13=4 12=0 11..10=3 9..7=ignore 6..5=3 4..2=ignore -c.j 1..0=1 15..13=5 12=ignore 11..2=ignore -c.beqz 1..0=1 15..13=6 12=ignore 11..2=ignore -c.bnez 1..0=1 15..13=7 12=ignore 11..2=ignore - -# C2 encoding space -c.slli 1..0=2 15..13=0 12=ignore 11..2=ignore -c.fldsp 1..0=2 15..13=1 12=ignore 11..2=ignore # c.lqsp for RV128 -c.lwsp 1..0=2 15..13=2 12=ignore 11..2=ignore -c.flwsp 1..0=2 15..13=3 12=ignore 11..2=ignore # c.ldsp for RV64 -c.mv 1..0=2 15..13=4 12=0 11..2=ignore # !rs2 = c.jr -c.add 1..0=2 15..13=4 12=1 11..2=ignore # !rs1 = c.ebreak; !rs2=c.jalr -c.fsdsp 1..0=2 15..13=5 12=ignore 11..2=ignore # c.sqsp for RV128 -c.swsp 1..0=2 15..13=6 12=ignore 11..2=ignore -c.fswsp 1..0=2 15..13=7 12=ignore 11..2=ignore # c.sdsp for RV64 diff --git a/rv128_c b/rv128_c new file mode 100644 index 0000000..beb6cd6 --- /dev/null +++ b/rv128_c @@ -0,0 +1,15 @@ +# quadrant 0 +c.lq rd_p rs1_p c_uimm9lo c_uimm9hi 1..0=0 15..13=1 +c.ld rd_p rs1_p c_uimm8lo c_uimm8hi 1..0=0 15..13=3 +c.sq rs1_p rs2_p c_uimm9hi c_uimm9lo 1..0=0 15..13=5 +c.sd rs1_p rs2_p c_uimm8hi c_uimm8lo 1..0=0 15..13=7 + +#quadrant 1 +c.addiw rd_rs1 c_imm6lo c_imm6hi 1..0=1 15..13=1 + +#quadrant 2 +c.lqsp rd c_uimm10sphi c_uimm10splo 1..0=2 15..13=1 +c.ldsp rd_n0 c_uimm9sphi c_uimm9splo 1..0=2 15..13=3 +c.sqsp c_rs2 c_uimm10sp_s 1..0=2 15..13=5 +c.sdsp c_rs2 c_uimm9sp_s 1..0=2 15..13=7 + diff --git a/rv32_c b/rv32_c new file mode 100644 index 0000000..d9a9072 --- /dev/null +++ b/rv32_c @@ -0,0 +1,5 @@ +# quadrant 1 +c.jal c_imm12 1..0=1 15..13=1 +$pseudo_op rv64_c::c.srli c.srli rd_rs1_p c_nzuimm5 1..0=1 15..13=4 12..10=0 +$pseudo_op rv64_c::c.srai c.srai rd_rs1_p c_nzuimm5 1..0=1 15..13=4 12..10=1 +$pseudo_op rv64_c::c.slli c.slli rd_rs1_n0 c_nzuimm6lo 1..0=2 15..12=0 diff --git a/rv32_c_f b/rv32_c_f new file mode 100644 index 0000000..8487c9a --- /dev/null +++ b/rv32_c_f @@ -0,0 +1,8 @@ +# quadrant 0 +c.flw rd_p rs1_p c_uimm7lo c_uimm7hi 1..0=0 15..13=3 +c.fsw rs1_p rs2_p c_uimm7lo c_uimm7hi 1..0=0 15..13=7 + +#quadrant 2 +c.flwsp rd c_uimm8sphi c_uimm8splo 1..0=2 15..13=3 +c.fswsp c_rs2 c_uimm8sp_s 1..0=2 15..13=7 + diff --git a/rv64_c b/rv64_c new file mode 100644 index 0000000..39d087a --- /dev/null +++ b/rv64_c @@ -0,0 +1,17 @@ +# quadrant 0 +c.ld rd_p rs1_p c_uimm8lo c_uimm8hi 1..0=0 15..13=3 +c.sd rs1_p rs2_p c_uimm8hi c_uimm8lo 1..0=0 15..13=7 + +#quadrant 1 +c.addiw rd_rs1 c_imm6lo c_imm6hi 1..0=1 15..13=1 +c.srli rd_rs1_p c_nzuimm6lo c_nzuimm6hi 1..0=1 15..13=4 11..10=0 +c.srai rd_rs1_p c_nzuimm6lo c_nzuimm6hi 1..0=1 15..13=4 11..10=1 +c.subw rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b111 6..5=0 +c.addw rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b111 6..5=1 + + +#quadrant 2 +c.slli rd_rs1_n0 c_nzuimm6hi c_nzuimm6lo 1..0=2 15..13=0 +c.ldsp rd_n0 c_uimm9sphi c_uimm9splo 1..0=2 15..13=3 +c.sdsp c_rs2 c_uimm9sp_s 1..0=2 15..13=7 + diff --git a/rv_c b/rv_c new file mode 100644 index 0000000..46b1e1c --- /dev/null +++ b/rv_c @@ -0,0 +1,32 @@ +# quadrant 0 +c.addi4spn rd_p c_nzuimm10 1..0=0 15..13=0 +c.lw rd_p rs1_p c_uimm7lo c_uimm7hi 1..0=0 15..13=2 +c.sw rs1_p rs2_p c_uimm7lo c_uimm7hi 1..0=0 15..13=6 + +#quadrant 1 +c.nop c_nzimm6hi c_nzimm6lo 1..0=1 15..13=0 11..7=0 +c.addi rd_rs1_n0 c_nzimm6lo c_nzimm6hi 1..0=1 15..13=0 +c.li rd c_imm6lo c_imm6hi 1..0=1 15..13=2 +c.addi16sp c_nzimm10hi c_nzimm10lo 1..0=1 15..13=3 11..7=2 +c.lui rd_n2 c_nzimm18hi c_nzimm18lo 1..0=1 15..13=3 +c.andi rd_rs1_p c_imm6hi c_imm6lo 1..0=1 15..13=4 11..10=2 +c.sub rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=0 +c.xor rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=1 +c.or rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=2 +c.and rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=3 +c.j c_imm12 1..0=1 15..13=5 +c.beqz rs1_p c_bimm9lo c_bimm9hi 1..0=1 15..13=6 +c.bnez rs1_p c_bimm9lo c_bimm9hi 1..0=1 15..13=7 + +#quadrant 2 +c.lwsp rd_n0 c_uimm8sphi c_uimm8splo 1..0=2 15..13=2 +c.jr rs1_n0 1..0=2 15..13=4 12=0 6..2=0 +c.mv rd c_rs2_n0 1..0=2 15..13=4 12=0 +c.ebreak 1..0=2 15..13=4 12=1 11..2=0 +c.jalr c_rs1_n0 1..0=2 15..13=4 12=1 6..2=0 +c.add rd_rs1 c_rs2_n0 1..0=2 15..13=4 12=1 +c.swsp c_rs2 c_uimm8sp_s 1..0=2 15..13=6 + + + + diff --git a/rv_c_d b/rv_c_d new file mode 100644 index 0000000..cd49b44 --- /dev/null +++ b/rv_c_d @@ -0,0 +1,8 @@ +#quadrant 0 +c.fld rd_p rs1_p c_uimm8lo c_uimm8hi 1..0=0 15..13=1 +c.fsd rs1_p rs2_p c_uimm8lo c_uimm8hi 1..0=0 15..13=5 + +#quadrant 2 +c.fldsp rd c_uimm9sphi c_uimm9splo 1..0=2 15..13=1 +c.fsdsp c_rs2 c_uimm9sp_s 1..0=2 15..13=5 + -- cgit v1.1 From c801c67946234562d5f7dad118118cac30274fa0 Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 17:39:54 +0530 Subject: migrate Zfh-extension opcodes - involves renaming and minor reordering to preserve latex tables --- opcodes-rv32d-zfh | 2 -- opcodes-rv32q-zfh | 2 -- opcodes-rv32zfh | 34 ---------------------------------- opcodes-rv64zfh | 7 ------- rv64_zfh | 7 +++++++ rv_d_zfh | 2 ++ rv_q_zfh | 2 ++ rv_zfh | 30 ++++++++++++++++++++++++++++++ 8 files changed, 41 insertions(+), 45 deletions(-) delete mode 100644 opcodes-rv32d-zfh delete mode 100644 opcodes-rv32q-zfh delete mode 100644 opcodes-rv32zfh delete mode 100644 opcodes-rv64zfh create mode 100644 rv64_zfh create mode 100644 rv_d_zfh create mode 100644 rv_q_zfh create mode 100644 rv_zfh diff --git a/opcodes-rv32d-zfh b/opcodes-rv32d-zfh deleted file mode 100644 index 02071ad..0000000 --- a/opcodes-rv32d-zfh +++ /dev/null @@ -1,2 +0,0 @@ -fcvt.h.d rd rs1 24..20=1 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 -fcvt.d.h rd rs1 24..20=2 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 diff --git a/opcodes-rv32q-zfh b/opcodes-rv32q-zfh deleted file mode 100644 index 265bfb4..0000000 --- a/opcodes-rv32q-zfh +++ /dev/null @@ -1,2 +0,0 @@ -fcvt.h.q rd rs1 24..20=3 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 -fcvt.q.h rd rs1 24..20=2 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 diff --git a/opcodes-rv32zfh b/opcodes-rv32zfh deleted file mode 100644 index 3a47671..0000000 --- a/opcodes-rv32zfh +++ /dev/null @@ -1,34 +0,0 @@ -fadd.h rd rs1 rs2 31..27=0x00 rm 26..25=2 6..2=0x14 1..0=3 -fsub.h rd rs1 rs2 31..27=0x01 rm 26..25=2 6..2=0x14 1..0=3 -fmul.h rd rs1 rs2 31..27=0x02 rm 26..25=2 6..2=0x14 1..0=3 -fdiv.h rd rs1 rs2 31..27=0x03 rm 26..25=2 6..2=0x14 1..0=3 -fsgnj.h rd rs1 rs2 31..27=0x04 14..12=0 26..25=2 6..2=0x14 1..0=3 -fsgnjn.h rd rs1 rs2 31..27=0x04 14..12=1 26..25=2 6..2=0x14 1..0=3 -fsgnjx.h rd rs1 rs2 31..27=0x04 14..12=2 26..25=2 6..2=0x14 1..0=3 -fmin.h rd rs1 rs2 31..27=0x05 14..12=0 26..25=2 6..2=0x14 1..0=3 -fmax.h rd rs1 rs2 31..27=0x05 14..12=1 26..25=2 6..2=0x14 1..0=3 -fcvt.h.s rd rs1 24..20=0 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 -fcvt.s.h rd rs1 24..20=2 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 -fsqrt.h rd rs1 24..20=0 31..27=0x0B rm 26..25=2 6..2=0x14 1..0=3 - -fle.h rd rs1 rs2 31..27=0x14 14..12=0 26..25=2 6..2=0x14 1..0=3 -flt.h rd rs1 rs2 31..27=0x14 14..12=1 26..25=2 6..2=0x14 1..0=3 -feq.h rd rs1 rs2 31..27=0x14 14..12=2 26..25=2 6..2=0x14 1..0=3 - -fcvt.w.h rd rs1 24..20=0 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 -fcvt.wu.h rd rs1 24..20=1 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 -fmv.x.h rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=2 6..2=0x14 1..0=3 -fclass.h rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=2 6..2=0x14 1..0=3 - -fcvt.h.w rd rs1 24..20=0 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 -fcvt.h.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 -fmv.h.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=2 6..2=0x14 1..0=3 - -flh rd rs1 imm12 14..12=1 6..2=0x01 1..0=3 - -fsh imm12hi rs1 rs2 imm12lo 14..12=1 6..2=0x09 1..0=3 - -fmadd.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x10 1..0=3 -fmsub.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x11 1..0=3 -fnmsub.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x12 1..0=3 -fnmadd.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x13 1..0=3 diff --git a/opcodes-rv64zfh b/opcodes-rv64zfh deleted file mode 100644 index 5cc9f25..0000000 --- a/opcodes-rv64zfh +++ /dev/null @@ -1,7 +0,0 @@ -# RV64Zfh additions to RV32Zfh - -fcvt.l.h rd rs1 24..20=2 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 -fcvt.lu.h rd rs1 24..20=3 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 - -fcvt.h.l rd rs1 24..20=2 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 -fcvt.h.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 diff --git a/rv64_zfh b/rv64_zfh new file mode 100644 index 0000000..5cc9f25 --- /dev/null +++ b/rv64_zfh @@ -0,0 +1,7 @@ +# RV64Zfh additions to RV32Zfh + +fcvt.l.h rd rs1 24..20=2 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 +fcvt.lu.h rd rs1 24..20=3 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 + +fcvt.h.l rd rs1 24..20=2 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 +fcvt.h.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 diff --git a/rv_d_zfh b/rv_d_zfh new file mode 100644 index 0000000..80d3765 --- /dev/null +++ b/rv_d_zfh @@ -0,0 +1,2 @@ +fcvt.d.h rd rs1 24..20=2 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 +fcvt.h.d rd rs1 24..20=1 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 diff --git a/rv_q_zfh b/rv_q_zfh new file mode 100644 index 0000000..24548d5 --- /dev/null +++ b/rv_q_zfh @@ -0,0 +1,2 @@ +fcvt.q.h rd rs1 24..20=2 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 +fcvt.h.q rd rs1 24..20=3 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 diff --git a/rv_zfh b/rv_zfh new file mode 100644 index 0000000..532dde5 --- /dev/null +++ b/rv_zfh @@ -0,0 +1,30 @@ +flh rd rs1 imm12 14..12=1 6..2=0x01 1..0=3 +fsh imm12hi rs1 rs2 imm12lo 14..12=1 6..2=0x09 1..0=3 +fmadd.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x10 1..0=3 +fmsub.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x11 1..0=3 +fnmsub.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x12 1..0=3 +fnmadd.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x13 1..0=3 +fadd.h rd rs1 rs2 31..27=0x00 rm 26..25=2 6..2=0x14 1..0=3 +fsub.h rd rs1 rs2 31..27=0x01 rm 26..25=2 6..2=0x14 1..0=3 +fmul.h rd rs1 rs2 31..27=0x02 rm 26..25=2 6..2=0x14 1..0=3 +fdiv.h rd rs1 rs2 31..27=0x03 rm 26..25=2 6..2=0x14 1..0=3 +fsqrt.h rd rs1 24..20=0 31..27=0x0B rm 26..25=2 6..2=0x14 1..0=3 +fsgnj.h rd rs1 rs2 31..27=0x04 14..12=0 26..25=2 6..2=0x14 1..0=3 +fsgnjn.h rd rs1 rs2 31..27=0x04 14..12=1 26..25=2 6..2=0x14 1..0=3 +fsgnjx.h rd rs1 rs2 31..27=0x04 14..12=2 26..25=2 6..2=0x14 1..0=3 +fmin.h rd rs1 rs2 31..27=0x05 14..12=0 26..25=2 6..2=0x14 1..0=3 +fmax.h rd rs1 rs2 31..27=0x05 14..12=1 26..25=2 6..2=0x14 1..0=3 +fcvt.s.h rd rs1 24..20=2 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.h.s rd rs1 24..20=0 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 + +feq.h rd rs1 rs2 31..27=0x14 14..12=2 26..25=2 6..2=0x14 1..0=3 +flt.h rd rs1 rs2 31..27=0x14 14..12=1 26..25=2 6..2=0x14 1..0=3 +fle.h rd rs1 rs2 31..27=0x14 14..12=0 26..25=2 6..2=0x14 1..0=3 +fclass.h rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=2 6..2=0x14 1..0=3 +fcvt.w.h rd rs1 24..20=0 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 +fcvt.wu.h rd rs1 24..20=1 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 +fmv.x.h rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=2 6..2=0x14 1..0=3 +fcvt.h.w rd rs1 24..20=0 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 +fcvt.h.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 +fmv.h.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=2 6..2=0x14 1..0=3 + -- cgit v1.1 From 6fa94f663801077eefde6a02117785d6506e2a99 Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 17:41:08 +0530 Subject: migrate H-extension opcodes - involves only renaming --- opcodes-rv32h | 14 -------------- opcodes-rv64h | 4 ---- rv64_h | 5 +++++ rv_h | 15 +++++++++++++++ 4 files changed, 20 insertions(+), 18 deletions(-) delete mode 100644 opcodes-rv32h delete mode 100644 opcodes-rv64h create mode 100644 rv64_h create mode 100644 rv_h diff --git a/opcodes-rv32h b/opcodes-rv32h deleted file mode 100644 index 84a361d..0000000 --- a/opcodes-rv32h +++ /dev/null @@ -1,14 +0,0 @@ -# Hypervisor extension -hfence.vvma 11..7=0 rs1 rs2 31..25=0x11 14..12=0 6..2=0x1C 1..0=3 -hfence.gvma 11..7=0 rs1 rs2 31..25=0x31 14..12=0 6..2=0x1C 1..0=3 - -hlv.b rd rs1 24..20=0x0 31..25=0x30 14..12=4 6..2=0x1C 1..0=3 -hlv.bu rd rs1 24..20=0x1 31..25=0x30 14..12=4 6..2=0x1C 1..0=3 -hlv.h rd rs1 24..20=0x0 31..25=0x32 14..12=4 6..2=0x1C 1..0=3 -hlv.hu rd rs1 24..20=0x1 31..25=0x32 14..12=4 6..2=0x1C 1..0=3 -hlvx.hu rd rs1 24..20=0x3 31..25=0x32 14..12=4 6..2=0x1C 1..0=3 -hlv.w rd rs1 24..20=0x0 31..25=0x34 14..12=4 6..2=0x1C 1..0=3 -hlvx.wu rd rs1 24..20=0x3 31..25=0x34 14..12=4 6..2=0x1C 1..0=3 -hsv.b 11..7=0 rs1 rs2 31..25=0x31 14..12=4 6..2=0x1C 1..0=3 -hsv.h 11..7=0 rs1 rs2 31..25=0x33 14..12=4 6..2=0x1C 1..0=3 -hsv.w 11..7=0 rs1 rs2 31..25=0x35 14..12=4 6..2=0x1C 1..0=3 diff --git a/opcodes-rv64h b/opcodes-rv64h deleted file mode 100644 index 75589e1..0000000 --- a/opcodes-rv64h +++ /dev/null @@ -1,4 +0,0 @@ -# Hypervisor extension -hlv.wu rd rs1 24..20=0x1 31..25=0x34 14..12=4 6..2=0x1C 1..0=3 -hlv.d rd rs1 24..20=0x0 31..25=0x36 14..12=4 6..2=0x1C 1..0=3 -hsv.d 11..7=0 rs1 rs2 31..25=0x37 14..12=4 6..2=0x1C 1..0=3 diff --git a/rv64_h b/rv64_h new file mode 100644 index 0000000..488dcd4 --- /dev/null +++ b/rv64_h @@ -0,0 +1,5 @@ +# Hypervisor extension +hlv.wu rd rs1 24..20=0x1 31..25=0x34 14..12=4 6..2=0x1C 1..0=3 +hlv.d rd rs1 24..20=0x0 31..25=0x36 14..12=4 6..2=0x1C 1..0=3 +hsv.d 11..7=0 rs1 rs2 31..25=0x37 14..12=4 6..2=0x1C 1..0=3 + diff --git a/rv_h b/rv_h new file mode 100644 index 0000000..63b9efc --- /dev/null +++ b/rv_h @@ -0,0 +1,15 @@ +# Hypervisor extension +hfence.vvma 11..7=0 rs1 rs2 31..25=0x11 14..12=0 6..2=0x1C 1..0=3 +hfence.gvma 11..7=0 rs1 rs2 31..25=0x31 14..12=0 6..2=0x1C 1..0=3 + +hlv.b rd rs1 24..20=0x0 31..25=0x30 14..12=4 6..2=0x1C 1..0=3 +hlv.bu rd rs1 24..20=0x1 31..25=0x30 14..12=4 6..2=0x1C 1..0=3 +hlv.h rd rs1 24..20=0x0 31..25=0x32 14..12=4 6..2=0x1C 1..0=3 +hlv.hu rd rs1 24..20=0x1 31..25=0x32 14..12=4 6..2=0x1C 1..0=3 +hlvx.hu rd rs1 24..20=0x3 31..25=0x32 14..12=4 6..2=0x1C 1..0=3 +hlv.w rd rs1 24..20=0x0 31..25=0x34 14..12=4 6..2=0x1C 1..0=3 +hlvx.wu rd rs1 24..20=0x3 31..25=0x34 14..12=4 6..2=0x1C 1..0=3 +hsv.b 11..7=0 rs1 rs2 31..25=0x31 14..12=4 6..2=0x1C 1..0=3 +hsv.h 11..7=0 rs1 rs2 31..25=0x33 14..12=4 6..2=0x1C 1..0=3 +hsv.w 11..7=0 rs1 rs2 31..25=0x35 14..12=4 6..2=0x1C 1..0=3 + -- cgit v1.1 From 9dda447e8d707cb47d0af8e7ac90443f06212313 Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 17:43:10 +0530 Subject: migrate Q-extension opcodes - renaming files and reordering to preserve latex-table order --- opcodes-rv32q | 38 -------------------------------------- opcodes-rv64q | 7 ------- rv64_q | 8 ++++++++ rv_q | 28 ++++++++++++++++++++++++++++ 4 files changed, 36 insertions(+), 45 deletions(-) delete mode 100644 opcodes-rv32q delete mode 100644 opcodes-rv64q create mode 100644 rv64_q create mode 100644 rv_q diff --git a/opcodes-rv32q b/opcodes-rv32q deleted file mode 100644 index c28fcbd..0000000 --- a/opcodes-rv32q +++ /dev/null @@ -1,38 +0,0 @@ -fadd.q rd rs1 rs2 31..27=0x00 rm 26..25=3 6..2=0x14 1..0=3 -fsub.q rd rs1 rs2 31..27=0x01 rm 26..25=3 6..2=0x14 1..0=3 -fmul.q rd rs1 rs2 31..27=0x02 rm 26..25=3 6..2=0x14 1..0=3 -fdiv.q rd rs1 rs2 31..27=0x03 rm 26..25=3 6..2=0x14 1..0=3 -fsgnj.q rd rs1 rs2 31..27=0x04 14..12=0 26..25=3 6..2=0x14 1..0=3 -fsgnjn.q rd rs1 rs2 31..27=0x04 14..12=1 26..25=3 6..2=0x14 1..0=3 -fsgnjx.q rd rs1 rs2 31..27=0x04 14..12=2 26..25=3 6..2=0x14 1..0=3 -fmin.q rd rs1 rs2 31..27=0x05 14..12=0 26..25=3 6..2=0x14 1..0=3 -fmax.q rd rs1 rs2 31..27=0x05 14..12=1 26..25=3 6..2=0x14 1..0=3 -fcvt.s.q rd rs1 24..20=3 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 -fcvt.q.s rd rs1 24..20=0 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 -fcvt.d.q rd rs1 24..20=3 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 -fcvt.q.d rd rs1 24..20=1 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 -fsqrt.q rd rs1 24..20=0 31..27=0x0B rm 26..25=3 6..2=0x14 1..0=3 - - - -fle.q rd rs1 rs2 31..27=0x14 14..12=0 26..25=3 6..2=0x14 1..0=3 -flt.q rd rs1 rs2 31..27=0x14 14..12=1 26..25=3 6..2=0x14 1..0=3 -feq.q rd rs1 rs2 31..27=0x14 14..12=2 26..25=3 6..2=0x14 1..0=3 - - -fcvt.w.q rd rs1 24..20=0 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 -fcvt.wu.q rd rs1 24..20=1 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 -fclass.q rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=3 6..2=0x14 1..0=3 - - -fcvt.q.w rd rs1 24..20=0 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 -fcvt.q.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 - -flq rd rs1 imm12 14..12=4 6..2=0x01 1..0=3 - -fsq imm12hi rs1 rs2 imm12lo 14..12=4 6..2=0x09 1..0=3 - -fmadd.q rd rs1 rs2 rs3 rm 26..25=3 6..2=0x10 1..0=3 -fmsub.q rd rs1 rs2 rs3 rm 26..25=3 6..2=0x11 1..0=3 -fnmsub.q rd rs1 rs2 rs3 rm 26..25=3 6..2=0x12 1..0=3 -fnmadd.q rd rs1 rs2 rs3 rm 26..25=3 6..2=0x13 1..0=3 diff --git a/opcodes-rv64q b/opcodes-rv64q deleted file mode 100644 index 571edf1..0000000 --- a/opcodes-rv64q +++ /dev/null @@ -1,7 +0,0 @@ -# RV64Q additions to RV32Q - -fcvt.l.q rd rs1 24..20=2 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 -fcvt.lu.q rd rs1 24..20=3 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 - -fcvt.q.l rd rs1 24..20=2 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 -fcvt.q.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 diff --git a/rv64_q b/rv64_q new file mode 100644 index 0000000..32019aa --- /dev/null +++ b/rv64_q @@ -0,0 +1,8 @@ +# RV64Q additions to RV32Q + +fcvt.l.q rd rs1 24..20=2 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 +fcvt.lu.q rd rs1 24..20=3 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 + +fcvt.q.l rd rs1 24..20=2 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 +fcvt.q.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 + diff --git a/rv_q b/rv_q new file mode 100644 index 0000000..298ae87 --- /dev/null +++ b/rv_q @@ -0,0 +1,28 @@ +flq rd rs1 imm12 14..12=4 6..2=0x01 1..0=3 +fsq imm12hi rs1 rs2 imm12lo 14..12=4 6..2=0x09 1..0=3 +fmadd.q rd rs1 rs2 rs3 rm 26..25=3 6..2=0x10 1..0=3 +fmsub.q rd rs1 rs2 rs3 rm 26..25=3 6..2=0x11 1..0=3 +fnmsub.q rd rs1 rs2 rs3 rm 26..25=3 6..2=0x12 1..0=3 +fnmadd.q rd rs1 rs2 rs3 rm 26..25=3 6..2=0x13 1..0=3 +fadd.q rd rs1 rs2 31..27=0x00 rm 26..25=3 6..2=0x14 1..0=3 +fsub.q rd rs1 rs2 31..27=0x01 rm 26..25=3 6..2=0x14 1..0=3 +fmul.q rd rs1 rs2 31..27=0x02 rm 26..25=3 6..2=0x14 1..0=3 +fdiv.q rd rs1 rs2 31..27=0x03 rm 26..25=3 6..2=0x14 1..0=3 +fsqrt.q rd rs1 24..20=0 31..27=0x0B rm 26..25=3 6..2=0x14 1..0=3 +fsgnj.q rd rs1 rs2 31..27=0x04 14..12=0 26..25=3 6..2=0x14 1..0=3 +fsgnjn.q rd rs1 rs2 31..27=0x04 14..12=1 26..25=3 6..2=0x14 1..0=3 +fsgnjx.q rd rs1 rs2 31..27=0x04 14..12=2 26..25=3 6..2=0x14 1..0=3 +fmin.q rd rs1 rs2 31..27=0x05 14..12=0 26..25=3 6..2=0x14 1..0=3 +fmax.q rd rs1 rs2 31..27=0x05 14..12=1 26..25=3 6..2=0x14 1..0=3 +fcvt.s.q rd rs1 24..20=3 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.q.s rd rs1 24..20=0 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 +fcvt.d.q rd rs1 24..20=3 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 +fcvt.q.d rd rs1 24..20=1 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 +feq.q rd rs1 rs2 31..27=0x14 14..12=2 26..25=3 6..2=0x14 1..0=3 +flt.q rd rs1 rs2 31..27=0x14 14..12=1 26..25=3 6..2=0x14 1..0=3 +fle.q rd rs1 rs2 31..27=0x14 14..12=0 26..25=3 6..2=0x14 1..0=3 +fclass.q rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=3 6..2=0x14 1..0=3 +fcvt.w.q rd rs1 24..20=0 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 +fcvt.wu.q rd rs1 24..20=1 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 +fcvt.q.w rd rs1 24..20=0 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 +fcvt.q.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 -- cgit v1.1 From f2fd4900318db42d2c7ab9495645a161ef8de4fd Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 17:47:06 +0530 Subject: migrate Zba-Extension opcodes - involves renaming of files --- opcodes-rv32zba | 3 --- opcodes-rv64zba | 9 --------- rv64_zba | 5 +++++ rv_zba | 3 +++ 4 files changed, 8 insertions(+), 12 deletions(-) delete mode 100644 opcodes-rv32zba delete mode 100644 opcodes-rv64zba create mode 100644 rv64_zba create mode 100644 rv_zba diff --git a/opcodes-rv32zba b/opcodes-rv32zba deleted file mode 100644 index 65eb420..0000000 --- a/opcodes-rv32zba +++ /dev/null @@ -1,3 +0,0 @@ -sh1add rd rs1 rs2 31..25=16 14..12=2 6..2=0x0C 1..0=3 -sh2add rd rs1 rs2 31..25=16 14..12=4 6..2=0x0C 1..0=3 -sh3add rd rs1 rs2 31..25=16 14..12=6 6..2=0x0C 1..0=3 diff --git a/opcodes-rv64zba b/opcodes-rv64zba deleted file mode 100644 index 28a1cfc..0000000 --- a/opcodes-rv64zba +++ /dev/null @@ -1,9 +0,0 @@ -# RV64Zba additions to RV32Zba - -slli.uw rd rs1 31..26=2 shamt 14..12=1 6..2=0x06 1..0=3 - -add.uw rd rs1 rs2 31..25=4 14..12=0 6..2=0x0E 1..0=3 - -sh1add.uw rd rs1 rs2 31..25=16 14..12=2 6..2=0x0E 1..0=3 -sh2add.uw rd rs1 rs2 31..25=16 14..12=4 6..2=0x0E 1..0=3 -sh3add.uw rd rs1 rs2 31..25=16 14..12=6 6..2=0x0E 1..0=3 diff --git a/rv64_zba b/rv64_zba new file mode 100644 index 0000000..52d9dcd --- /dev/null +++ b/rv64_zba @@ -0,0 +1,5 @@ +add.uw rd rs1 rs2 31..25=4 14..12=0 6..2=0x0E 1..0=3 +sh1add.uw rd rs1 rs2 31..25=16 14..12=2 6..2=0x0E 1..0=3 +sh2add.uw rd rs1 rs2 31..25=16 14..12=4 6..2=0x0E 1..0=3 +sh3add.uw rd rs1 rs2 31..25=16 14..12=6 6..2=0x0E 1..0=3 +slli.uw rd rs1 31..26=2 shamt 14..12=1 6..2=0x06 1..0=3 diff --git a/rv_zba b/rv_zba new file mode 100644 index 0000000..65eb420 --- /dev/null +++ b/rv_zba @@ -0,0 +1,3 @@ +sh1add rd rs1 rs2 31..25=16 14..12=2 6..2=0x0C 1..0=3 +sh2add rd rs1 rs2 31..25=16 14..12=4 6..2=0x0C 1..0=3 +sh3add rd rs1 rs2 31..25=16 14..12=6 6..2=0x0C 1..0=3 -- cgit v1.1 From 5c2670bd8fb784f479cfb56173e3cf77eec28bf4 Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 17:53:54 +0530 Subject: migrate Zbb-Extension opcodes - aliases have been revised to use $pseudo_op syntax - split the instructions into multiple files as per new file naming policy - some pseudo ops depend on unratified instructions. --- opcodes-rv32zbb | 24 ------------------------ opcodes-rv64zbb | 13 ------------- rv32_zbb | 3 +++ rv64_zbb | 9 +++++++++ rv_zbb | 15 +++++++++++++++ 5 files changed, 27 insertions(+), 37 deletions(-) delete mode 100644 opcodes-rv32zbb delete mode 100644 opcodes-rv64zbb create mode 100644 rv32_zbb create mode 100644 rv64_zbb create mode 100644 rv_zbb diff --git a/opcodes-rv32zbb b/opcodes-rv32zbb deleted file mode 100644 index ed80dfe..0000000 --- a/opcodes-rv32zbb +++ /dev/null @@ -1,24 +0,0 @@ -andn rd rs1 rs2 31..25=32 14..12=7 6..2=0x0C 1..0=3 -orn rd rs1 rs2 31..25=32 14..12=6 6..2=0x0C 1..0=3 -xnor rd rs1 rs2 31..25=32 14..12=4 6..2=0x0C 1..0=3 - -rol rd rs1 rs2 31..25=48 14..12=1 6..2=0x0C 1..0=3 -ror rd rs1 rs2 31..25=48 14..12=5 6..2=0x0C 1..0=3 - -rori rd rs1 31..26=24 shamt 14..12=5 6..2=0x04 1..0=3 - -clz rd rs1 31..20=0x600 14..12=1 6..2=0x04 1..0=3 -ctz rd rs1 31..20=0x601 14..12=1 6..2=0x04 1..0=3 -cpop rd rs1 31..20=0x602 14..12=1 6..2=0x04 1..0=3 -sext.b rd rs1 31..20=0x604 14..12=1 6..2=0x04 1..0=3 -sext.h rd rs1 31..20=0x605 14..12=1 6..2=0x04 1..0=3 - -min rd rs1 rs2 31..25=5 14..12=4 6..2=0x0C 1..0=3 -minu rd rs1 rs2 31..25=5 14..12=5 6..2=0x0C 1..0=3 -max rd rs1 rs2 31..25=5 14..12=6 6..2=0x0C 1..0=3 -maxu rd rs1 rs2 31..25=5 14..12=7 6..2=0x0C 1..0=3 - -orc.b rd rs1 31..26=10 25..20=7 14..12=5 6..2=0x04 1..0=3 - -@rev8.rv32 rd rs1 31..26=26 25..20=24 14..12=5 6..2=0x04 1..0=3 -@zext.h.rv32 rd rs1 31..25=4 24..20=0 14..12=4 6..2=0x0C 1..0=3 diff --git a/opcodes-rv64zbb b/opcodes-rv64zbb deleted file mode 100644 index c2ab552..0000000 --- a/opcodes-rv64zbb +++ /dev/null @@ -1,13 +0,0 @@ -# RV64Zbb additions to RV32Zbb - -rolw rd rs1 rs2 31..25=48 14..12=1 6..2=0x0E 1..0=3 -rorw rd rs1 rs2 31..25=48 14..12=5 6..2=0x0E 1..0=3 - -roriw rd rs1 31..26=24 25=0 shamtw 14..12=5 6..2=0x06 1..0=3 - -clzw rd rs1 31..20=0x600 14..12=1 6..2=0x06 1..0=3 -ctzw rd rs1 31..20=0x601 14..12=1 6..2=0x06 1..0=3 -cpopw rd rs1 31..20=0x602 14..12=1 6..2=0x06 1..0=3 - -rev8 rd rs1 31..26=26 25..20=56 14..12=5 6..2=0x04 1..0=3 -@zext.h rd rs1 31..25=4 24..20=0 14..12=4 6..2=0x0E 1..0=3 diff --git a/rv32_zbb b/rv32_zbb new file mode 100644 index 0000000..cadea09 --- /dev/null +++ b/rv32_zbb @@ -0,0 +1,3 @@ +$pseudo_op rv_zbe::pack zext.h rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..0=0x33 +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x698 14..12=5 6..0=0x13 +$pseudo_op rv64_zbb::rori rori rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 diff --git a/rv64_zbb b/rv64_zbb new file mode 100644 index 0000000..fc19561 --- /dev/null +++ b/rv64_zbb @@ -0,0 +1,9 @@ +clzw rd rs1 31..20=0x600 14..12=1 6..2=0x06 1..0=3 +ctzw rd rs1 31..20=0x601 14..12=1 6..2=0x06 1..0=3 +cpopw rd rs1 31..20=0x602 14..12=1 6..2=0x06 1..0=3 +rolw rd rs1 rs2 31..25=0x30 14..12=1 6..2=0x0E 1..0=3 +rorw rd rs1 rs2 31..25=0x30 14..12=5 6..2=0x0E 1..0=3 +roriw rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x06 1..0=3 +rori rd rs1 31..26=0x18 shamt 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbe::packw zext.h rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..2=0xE 1..0=0x3 +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 diff --git a/rv_zbb b/rv_zbb new file mode 100644 index 0000000..9f384f6 --- /dev/null +++ b/rv_zbb @@ -0,0 +1,15 @@ +andn rd rs1 rs2 31..25=32 14..12=7 6..2=0x0C 1..0=3 +orn rd rs1 rs2 31..25=32 14..12=6 6..2=0x0C 1..0=3 +xnor rd rs1 rs2 31..25=32 14..12=4 6..2=0x0C 1..0=3 +clz rd rs1 31..20=0x600 14..12=1 6..2=0x04 1..0=3 +ctz rd rs1 31..20=0x601 14..12=1 6..2=0x04 1..0=3 +cpop rd rs1 31..20=0x602 14..12=1 6..2=0x04 1..0=3 +max rd rs1 rs2 31..25=5 14..12=6 6..2=0x0C 1..0=3 +maxu rd rs1 rs2 31..25=5 14..12=7 6..2=0x0C 1..0=3 +min rd rs1 rs2 31..25=5 14..12=4 6..2=0x0C 1..0=3 +minu rd rs1 rs2 31..25=5 14..12=5 6..2=0x0C 1..0=3 +sext.b rd rs1 31..20=0x604 14..12=1 6..2=0x04 1..0=3 +sext.h rd rs1 31..20=0x605 14..12=1 6..2=0x04 1..0=3 +rol rd rs1 rs2 31..25=0x30 14..12=1 6..2=0x0C 1..0=3 +ror rd rs1 rs2 31..25=0x30 14..12=5 6..2=0x0C 1..0=3 +$pseudo_op rv64_zbp::gorci orc.b rd rs1 31..20=0x287 14..12=0x5 6..0=0x13 -- cgit v1.1 From 7cc95c1fd39fb5596718e6c3211f7dbc84c19322 Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 17:54:16 +0530 Subject: migrate Zbc-Extension --- opcodes-rv32zbc | 3 --- rv_zbc | 4 ++++ 2 files changed, 4 insertions(+), 3 deletions(-) delete mode 100644 opcodes-rv32zbc create mode 100644 rv_zbc diff --git a/opcodes-rv32zbc b/opcodes-rv32zbc deleted file mode 100644 index 821518b..0000000 --- a/opcodes-rv32zbc +++ /dev/null @@ -1,3 +0,0 @@ -clmul rd rs1 rs2 31..25=5 14..12=1 6..2=0x0C 1..0=3 -clmulr rd rs1 rs2 31..25=5 14..12=2 6..2=0x0C 1..0=3 -clmulh rd rs1 rs2 31..25=5 14..12=3 6..2=0x0C 1..0=3 diff --git a/rv_zbc b/rv_zbc new file mode 100644 index 0000000..c2494bd --- /dev/null +++ b/rv_zbc @@ -0,0 +1,4 @@ +clmul rd rs1 rs2 31..25=5 14..12=1 6..2=0x0C 1..0=3 +clmulr rd rs1 rs2 31..25=5 14..12=2 6..2=0x0C 1..0=3 +clmulh rd rs1 rs2 31..25=5 14..12=3 6..2=0x0C 1..0=3 + -- cgit v1.1 From 5e7610c70fe8afaa5dadbc249e9f77117ee30e32 Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 17:56:28 +0530 Subject: migrate Zbs-Extension opcodes - split instructions as per new file naming policy - here the 32-bit ops are considered pseudo_ops of the 64-bit equivalents as they only differ in one-bit. --- opcodes-rv32zbs | 9 --------- rv32_zbs | 5 +++++ rv64_zbs | 5 +++++ rv_zbs | 5 +++++ 4 files changed, 15 insertions(+), 9 deletions(-) delete mode 100644 opcodes-rv32zbs create mode 100644 rv32_zbs create mode 100644 rv64_zbs create mode 100644 rv_zbs diff --git a/opcodes-rv32zbs b/opcodes-rv32zbs deleted file mode 100644 index 1de3fc2..0000000 --- a/opcodes-rv32zbs +++ /dev/null @@ -1,9 +0,0 @@ -bclr rd rs1 rs2 31..25=36 14..12=1 6..2=0x0C 1..0=3 -bset rd rs1 rs2 31..25=20 14..12=1 6..2=0x0C 1..0=3 -binv rd rs1 rs2 31..25=52 14..12=1 6..2=0x0C 1..0=3 -bext rd rs1 rs2 31..25=36 14..12=5 6..2=0x0C 1..0=3 - -bclri rd rs1 31..26=18 shamt 14..12=1 6..2=0x04 1..0=3 -bseti rd rs1 31..26=10 shamt 14..12=1 6..2=0x04 1..0=3 -binvi rd rs1 31..26=26 shamt 14..12=1 6..2=0x04 1..0=3 -bexti rd rs1 31..26=18 shamt 14..12=5 6..2=0x04 1..0=3 diff --git a/rv32_zbs b/rv32_zbs new file mode 100644 index 0000000..14ac441 --- /dev/null +++ b/rv32_zbs @@ -0,0 +1,5 @@ +$pseudo_op rv64_zbs::bclri bclri rd rs1 31..25=0x24 shamtw 14..12=1 6..2=0x04 1..0=3 +$pseudo_op rv64_zbs::bexti bexti rd rs1 31..25=0x24 shamtw 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbs::binvi binvi rd rs1 31..25=0x34 shamtw 14..12=1 6..2=0x04 1..0=3 +$pseudo_op rv64_zbs::bseti bseti rd rs1 31..25=0x14 shamtw 14..12=1 6..2=0x04 1..0=3 + diff --git a/rv64_zbs b/rv64_zbs new file mode 100644 index 0000000..d3203a6 --- /dev/null +++ b/rv64_zbs @@ -0,0 +1,5 @@ +bclri rd rs1 31..26=0x12 shamt 14..12=1 6..2=0x04 1..0=3 +bexti rd rs1 31..26=0x12 shamt 14..12=5 6..2=0x04 1..0=3 +binvi rd rs1 31..26=0x1a shamt 14..12=1 6..2=0x04 1..0=3 +bseti rd rs1 31..26=0x0a shamt 14..12=1 6..2=0x04 1..0=3 + diff --git a/rv_zbs b/rv_zbs new file mode 100644 index 0000000..1949072 --- /dev/null +++ b/rv_zbs @@ -0,0 +1,5 @@ +bclr rd rs1 rs2 31..25=0x24 14..12=1 6..2=0x0C 1..0=3 +bext rd rs1 rs2 31..25=36 14..12=5 6..2=0x0C 1..0=3 +binv rd rs1 rs2 31..25=52 14..12=1 6..2=0x0C 1..0=3 +bset rd rs1 rs2 31..25=20 14..12=1 6..2=0x0C 1..0=3 + -- cgit v1.1 From cc1bc440b3e338b366674faff531c6ffadb9b239 Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 18:00:28 +0530 Subject: migrate Zifencei-Extension opcode --- rv_zifencei | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 rv_zifencei diff --git a/rv_zifencei b/rv_zifencei new file mode 100644 index 0000000..8f9ec85 --- /dev/null +++ b/rv_zifencei @@ -0,0 +1,2 @@ +fence.i imm12 rs1 14..12=1 rd 6..2=0x03 1..0=3 + -- cgit v1.1 From cf2bef3f0e52f95f9dfc9ce4ac8ff8ced92a26ac Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 18:02:38 +0530 Subject: migrate Zicsr-Extension opcodes - renamed the variable imm12 to csr to match the latex-table entries. --- opcodes-system | 8 -------- rv_zicsr | 7 +++++++ 2 files changed, 7 insertions(+), 8 deletions(-) create mode 100644 rv_zicsr diff --git a/opcodes-system b/opcodes-system index aa26e38..1721905 100644 --- a/opcodes-system +++ b/opcodes-system @@ -1,14 +1,6 @@ # SYSTEM -ecall 11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3 -ebreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3 sret 11..7=0 19..15=0 31..20=0x102 14..12=0 6..2=0x1C 1..0=3 mret 11..7=0 19..15=0 31..20=0x302 14..12=0 6..2=0x1C 1..0=3 dret 11..7=0 19..15=0 31..20=0x7b2 14..12=0 6..2=0x1C 1..0=3 sfence.vma 11..7=0 rs1 rs2 31..25=0x09 14..12=0 6..2=0x1C 1..0=3 wfi 11..7=0 19..15=0 31..20=0x105 14..12=0 6..2=0x1C 1..0=3 -csrrw rd rs1 imm12 14..12=1 6..2=0x1C 1..0=3 -csrrs rd rs1 imm12 14..12=2 6..2=0x1C 1..0=3 -csrrc rd rs1 imm12 14..12=3 6..2=0x1C 1..0=3 -csrrwi rd rs1 imm12 14..12=5 6..2=0x1C 1..0=3 -csrrsi rd rs1 imm12 14..12=6 6..2=0x1C 1..0=3 -csrrci rd rs1 imm12 14..12=7 6..2=0x1C 1..0=3 diff --git a/rv_zicsr b/rv_zicsr new file mode 100644 index 0000000..5c3e338 --- /dev/null +++ b/rv_zicsr @@ -0,0 +1,7 @@ +csrrw rd rs1 csr 14..12=1 6..2=0x1C 1..0=3 +csrrs rd rs1 csr 14..12=2 6..2=0x1C 1..0=3 +csrrc rd rs1 csr 14..12=3 6..2=0x1C 1..0=3 +csrrwi rd csr zimm 14..12=5 6..2=0x1C 1..0=3 +csrrsi rd csr zimm 14..12=6 6..2=0x1C 1..0=3 +csrrci rd csr zimm 14..12=7 6..2=0x1C 1..0=3 + -- cgit v1.1 From 2a7be7ea181304f99e90a0180e026761501fa5ac Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 18:04:04 +0530 Subject: migrate system opcodes --- opcodes-system | 3 --- rv_system | 5 +++++ 2 files changed, 5 insertions(+), 3 deletions(-) create mode 100644 rv_system diff --git a/opcodes-system b/opcodes-system index 1721905..e77b0f6 100644 --- a/opcodes-system +++ b/opcodes-system @@ -1,6 +1,3 @@ # SYSTEM sret 11..7=0 19..15=0 31..20=0x102 14..12=0 6..2=0x1C 1..0=3 -mret 11..7=0 19..15=0 31..20=0x302 14..12=0 6..2=0x1C 1..0=3 -dret 11..7=0 19..15=0 31..20=0x7b2 14..12=0 6..2=0x1C 1..0=3 sfence.vma 11..7=0 rs1 rs2 31..25=0x09 14..12=0 6..2=0x1C 1..0=3 -wfi 11..7=0 19..15=0 31..20=0x105 14..12=0 6..2=0x1C 1..0=3 diff --git a/rv_system b/rv_system new file mode 100644 index 0000000..f94c4cf --- /dev/null +++ b/rv_system @@ -0,0 +1,5 @@ +# SYSTEM +mret 11..7=0 19..15=0 31..20=0x302 14..12=0 6..2=0x1C 1..0=3 +dret 11..7=0 19..15=0 31..20=0x7b2 14..12=0 6..2=0x1C 1..0=3 +wfi 11..7=0 19..15=0 31..20=0x105 14..12=0 6..2=0x1C 1..0=3 + -- cgit v1.1 From 5a77af8414f8982f06ee6a6ab2e5f07f836e4406 Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 18:04:32 +0530 Subject: migrate S-extension opcodes --- opcodes-system | 3 --- rv_s | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-) delete mode 100644 opcodes-system create mode 100644 rv_s diff --git a/opcodes-system b/opcodes-system deleted file mode 100644 index e77b0f6..0000000 --- a/opcodes-system +++ /dev/null @@ -1,3 +0,0 @@ -# SYSTEM -sret 11..7=0 19..15=0 31..20=0x102 14..12=0 6..2=0x1C 1..0=3 -sfence.vma 11..7=0 rs1 rs2 31..25=0x09 14..12=0 6..2=0x1C 1..0=3 diff --git a/rv_s b/rv_s new file mode 100644 index 0000000..25f3532 --- /dev/null +++ b/rv_s @@ -0,0 +1,3 @@ +sfence.vma 11..7=0 rs1 rs2 31..25=0x09 14..12=0 6..2=0x1C 1..0=3 +sret 11..7=0 19..15=0 31..20=0x102 14..12=0 6..2=0x1C 1..0=3 + -- cgit v1.1 From 2d51853d6aa09c03a4c8a3420bff611b72583bde Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 18:05:08 +0530 Subject: migrate Svinval-Extension --- opcodes-svinval | 6 ------ rv_svinval | 7 +++++++ 2 files changed, 7 insertions(+), 6 deletions(-) delete mode 100644 opcodes-svinval create mode 100644 rv_svinval diff --git a/opcodes-svinval b/opcodes-svinval deleted file mode 100644 index 152835b..0000000 --- a/opcodes-svinval +++ /dev/null @@ -1,6 +0,0 @@ -# Svinval -sinval.vma 11..7=0 rs1 rs2 31..25=0x0b 14..12=0 6..2=0x1C 1..0=3 -sfence.w.inval 11..7=0 19..15=0x0 24..20=0x0 31..25=0x0c 14..12=0 6..2=0x1C 1..0=3 -sfence.inval.ir 11..7=0 19..15=0x0 24..20=0x1 31..25=0x0c 14..12=0 6..2=0x1C 1..0=3 -hinval.vvma 11..7=0 rs1 rs2 31..25=0x13 14..12=0 6..2=0x1C 1..0=3 -hinval.gvma 11..7=0 rs1 rs2 31..25=0x33 14..12=0 6..2=0x1C 1..0=3 diff --git a/rv_svinval b/rv_svinval new file mode 100644 index 0000000..b35ae7c --- /dev/null +++ b/rv_svinval @@ -0,0 +1,7 @@ +# Svinval +sinval.vma 11..7=0 rs1 rs2 31..25=0x0b 14..12=0 6..2=0x1C 1..0=3 +sfence.w.inval 11..7=0 19..15=0x0 24..20=0x0 31..25=0x0c 14..12=0 6..2=0x1C 1..0=3 +sfence.inval.ir 11..7=0 19..15=0x0 24..20=0x1 31..25=0x0c 14..12=0 6..2=0x1C 1..0=3 +hinval.vvma 11..7=0 rs1 rs2 31..25=0x13 14..12=0 6..2=0x1C 1..0=3 +hinval.gvma 11..7=0 rs1 rs2 31..25=0x33 14..12=0 6..2=0x1C 1..0=3 + -- cgit v1.1 From 816ff492f499a37db4f5a22c56bf8d50d91a8dbf Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 18:07:38 +0530 Subject: migrating Zicbo-Extension - all prefetch insructions have been made appropriate pseudo_ops of ori instruction --- opcodes-zicbo | 12 ------------ rv_zicbo | 12 ++++++++++++ 2 files changed, 12 insertions(+), 12 deletions(-) delete mode 100644 opcodes-zicbo create mode 100644 rv_zicbo diff --git a/opcodes-zicbo b/opcodes-zicbo deleted file mode 100644 index 13e1668..0000000 --- a/opcodes-zicbo +++ /dev/null @@ -1,12 +0,0 @@ -# Zicbom: cache-block management instructions -cbo.clean rs1 31..20=1 14..12=2 11..7=0 6..2=0x03 1..0=3 -cbo.flush rs1 31..20=2 14..12=2 11..7=0 6..2=0x03 1..0=3 -cbo.inval rs1 31..20=0 14..12=2 11..7=0 6..2=0x03 1..0=3 - -# Zicboz: cache-block zero instruction -cbo.zero rs1 31..20=4 14..12=2 11..7=0 6..2=0x03 1..0=3 - -# Zicbop: prefetch hint pseudoinstructions -@prefetch.i rs1 imm12hi 24..20=0 14..12=6 11..7=0 6..2=0x04 1..0=3 -@prefetch.r rs1 imm12hi 24..20=1 14..12=6 11..7=0 6..2=0x04 1..0=3 -@prefetch.w rs1 imm12hi 24..20=3 14..12=6 11..7=0 6..2=0x04 1..0=3 diff --git a/rv_zicbo b/rv_zicbo new file mode 100644 index 0000000..65a4567 --- /dev/null +++ b/rv_zicbo @@ -0,0 +1,12 @@ +# Zicbom: cache-block management instructions +cbo.clean rs1 31..20=1 14..12=2 11..7=0 6..2=0x03 1..0=3 +cbo.flush rs1 31..20=2 14..12=2 11..7=0 6..2=0x03 1..0=3 +cbo.inval rs1 31..20=0 14..12=2 11..7=0 6..2=0x03 1..0=3 + +# Zicboz: cache-block zero instruction +cbo.zero rs1 31..20=4 14..12=2 11..7=0 6..2=0x03 1..0=3 + +# Zicbop: prefetch hint pseudoinstructions +$pseudo_op rv_i::ori prefetch.i rs1 imm12hi 24..20=0 14..12=6 11..7=0 6..2=0x04 1..0=3 +$pseudo_op rv_i::ori prefetch.r rs1 imm12hi 24..20=1 14..12=6 11..7=0 6..2=0x04 1..0=3 +$pseudo_op rv_i::ori prefetch.w rs1 imm12hi 24..20=3 14..12=6 11..7=0 6..2=0x04 1..0=3 -- cgit v1.1 From 9f373585534a390bb320db297626f96e0d022134 Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 18:33:27 +0530 Subject: migrate V-extension opcodes --- opcodes-rvv | 528 ------------------------------------------------------------ rv_v | 528 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 528 insertions(+), 528 deletions(-) delete mode 100644 opcodes-rvv create mode 100644 rv_v diff --git a/opcodes-rvv b/opcodes-rvv deleted file mode 100644 index 29a0ff8..0000000 --- a/opcodes-rvv +++ /dev/null @@ -1,528 +0,0 @@ -# format of a line in this file: -# -# -# is given by specifying one or more range/value pairs: -# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) -# -# is one of vd, vs3, vs1, vs2, vm, nf, wd, simm5, zimm10, zimm11 - -# configuration setting -# https://github.com/riscv/riscv-v-spec/blob/master/vcfg-format.adoc -vsetivli 31=1 30=1 zimm10 zimm 14..12=0x7 rd 6..0=0x57 -vsetvli 31=0 zimm11 rs1 14..12=0x7 rd 6..0=0x57 -vsetvl 31=1 30..25=0x0 rs2 rs1 14..12=0x7 rd 6..0=0x57 - -# -# Vector Loads and Store -# https://github.com/riscv/riscv-v-spec/blob/master/vmem-format.adoc -# -# Vector Unit-Stride Instructions (including segment part) -# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#74-vector-unit-stride-instructions -vlm.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vd 6..0=0x07 -vsm.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vs3 6..0=0x27 -vle8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07 -vle16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07 -vle32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07 -vle64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07 -vle128.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07 -vle256.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07 -vle512.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07 -vle1024.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07 -vse8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27 -vse16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27 -vse32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27 -vse64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27 -vse128.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27 -vse256.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27 -vse512.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27 -vse1024.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27 - -# Vector Indexed-Unordered Instructions (including segment part) -# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#76-vector-indexed-instructions -vluxei8.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 -vluxei16.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 -vluxei32.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 -vluxei64.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 -vluxei128.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 -vluxei256.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 -vluxei512.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 -vluxei1024.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 -vsuxei8.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 -vsuxei16.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 -vsuxei32.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 -vsuxei64.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 -vsuxei128.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 -vsuxei256.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 -vsuxei512.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 -vsuxei1024.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 - -# Vector Strided Instructions (including segment part) -# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#75-vector-strided-instructions -vlse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07 -vlse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07 -vlse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07 -vlse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07 -vlse128.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07 -vlse256.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07 -vlse512.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07 -vlse1024.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07 -vsse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27 -vsse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27 -vsse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27 -vsse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27 -vsse128.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27 -vsse256.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27 -vsse512.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27 -vsse1024.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27 - -# Vector Indexed-Ordered Instructions (including segment part) -# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#76-vector-indexed-instructions -vloxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 -vloxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 -vloxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 -vloxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 -vloxei128.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 -vloxei256.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 -vloxei512.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 -vloxei1024.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 -vsoxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 -vsoxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 -vsoxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 -vsoxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 -vsoxei128.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 -vsoxei256.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 -vsoxei512.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 -vsoxei1024.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 - -# Unit-stride F31..29=0ault-Only-First Loads -# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#77-unit-stride-fault-only-first-loads -vle8ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07 -vle16ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07 -vle32ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07 -vle64ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07 -vle128ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07 -vle256ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07 -vle512ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07 -vle1024ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07 - -# Vector Load/Store Whole Registers -# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#79-vector-loadstore-whole-register-instructions -vl1re8.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 -vl1re16.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 -vl1re32.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 -vl1re64.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 -vl2re8.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 -vl2re16.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 -vl2re32.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 -vl2re64.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 -vl4re8.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 -vl4re16.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 -vl4re32.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 -vl4re64.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 -vl8re8.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 -vl8re16.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 -vl8re32.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 -vl8re64.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 -vs1r.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 -vs2r.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 -vs4r.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 -vs8r.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 - -# Vector Floating-Point Instructions -# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#14-vector-floating-point-instructions -# OPFVF -vfadd.vf 31..26=0x00 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfsub.vf 31..26=0x02 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfmin.vf 31..26=0x04 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfmax.vf 31..26=0x06 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfsgnj.vf 31..26=0x08 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfsgnjn.vf 31..26=0x09 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfsgnjx.vf 31..26=0x0a vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfslide1up.vf 31..26=0x0e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfslide1down.vf 31..26=0x0f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfmv.s.f 31..26=0x10 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57 - -vfmerge.vfm 31..26=0x17 25=0 vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfmv.v.f 31..26=0x17 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57 -vmfeq.vf 31..26=0x18 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vmfle.vf 31..26=0x19 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vmflt.vf 31..26=0x1b vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vmfne.vf 31..26=0x1c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vmfgt.vf 31..26=0x1d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vmfge.vf 31..26=0x1f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 - -vfdiv.vf 31..26=0x20 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfrdiv.vf 31..26=0x21 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfmul.vf 31..26=0x24 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfrsub.vf 31..26=0x27 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfmadd.vf 31..26=0x28 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfnmadd.vf 31..26=0x29 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfmsub.vf 31..26=0x2a vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfnmsub.vf 31..26=0x2b vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfmacc.vf 31..26=0x2c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfnmacc.vf 31..26=0x2d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfmsac.vf 31..26=0x2e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfnmsac.vf 31..26=0x2f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 - -vfwadd.vf 31..26=0x30 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfwsub.vf 31..26=0x32 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfwadd.wf 31..26=0x34 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfwsub.wf 31..26=0x36 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfwmul.vf 31..26=0x38 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfwmacc.vf 31..26=0x3c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfwnmacc.vf 31..26=0x3d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfwmsac.vf 31..26=0x3e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfwnmsac.vf 31..26=0x3f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 - -# OPFVV -vfadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfredusum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfsub.vv 31..26=0x02 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfredosum.vs 31..26=0x03 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfmin.vv 31..26=0x04 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfredmin.vs 31..26=0x05 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfmax.vv 31..26=0x06 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfsgnj.vv 31..26=0x08 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfsgnjn.vv 31..26=0x09 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfsgnjx.vv 31..26=0x0a vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfmv.f.s 31..26=0x10 25=1 vs2 19..15=0 14..12=0x1 rd 6..0=0x57 - -vmfeq.vv 31..26=0x18 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vmfle.vv 31..26=0x19 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vmflt.vv 31..26=0x1b vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vmfne.vv 31..26=0x1c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 - -vfdiv.vv 31..26=0x20 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfmul.vv 31..26=0x24 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfmadd.vv 31..26=0x28 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfnmadd.vv 31..26=0x29 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfmsub.vv 31..26=0x2a vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfnmsub.vv 31..26=0x2b vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfmacc.vv 31..26=0x2c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfnmacc.vv 31..26=0x2d vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfmsac.vv 31..26=0x2e vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfnmsac.vv 31..26=0x2f vm vs2 vs1 14..12=0x1 vd 6..0=0x57 - -vfcvt.xu.f.v 31..26=0x12 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57 -vfcvt.x.f.v 31..26=0x12 vm vs2 19..15=0x01 14..12=0x1 vd 6..0=0x57 -vfcvt.f.xu.v 31..26=0x12 vm vs2 19..15=0x02 14..12=0x1 vd 6..0=0x57 -vfcvt.f.x.v 31..26=0x12 vm vs2 19..15=0x03 14..12=0x1 vd 6..0=0x57 -vfcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x06 14..12=0x1 vd 6..0=0x57 -vfcvt.rtz.x.f.v 31..26=0x12 vm vs2 19..15=0x07 14..12=0x1 vd 6..0=0x57 - -vfwcvt.xu.f.v 31..26=0x12 vm vs2 19..15=0x08 14..12=0x1 vd 6..0=0x57 -vfwcvt.x.f.v 31..26=0x12 vm vs2 19..15=0x09 14..12=0x1 vd 6..0=0x57 -vfwcvt.f.xu.v 31..26=0x12 vm vs2 19..15=0x0A 14..12=0x1 vd 6..0=0x57 -vfwcvt.f.x.v 31..26=0x12 vm vs2 19..15=0x0B 14..12=0x1 vd 6..0=0x57 -vfwcvt.f.f.v 31..26=0x12 vm vs2 19..15=0x0C 14..12=0x1 vd 6..0=0x57 -vfwcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x0E 14..12=0x1 vd 6..0=0x57 -vfwcvt.rtz.x.f.v 31..26=0x12 vm vs2 19..15=0x0F 14..12=0x1 vd 6..0=0x57 - -vfncvt.xu.f.w 31..26=0x12 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57 -vfncvt.x.f.w 31..26=0x12 vm vs2 19..15=0x11 14..12=0x1 vd 6..0=0x57 -vfncvt.f.xu.w 31..26=0x12 vm vs2 19..15=0x12 14..12=0x1 vd 6..0=0x57 -vfncvt.f.x.w 31..26=0x12 vm vs2 19..15=0x13 14..12=0x1 vd 6..0=0x57 -vfncvt.f.f.w 31..26=0x12 vm vs2 19..15=0x14 14..12=0x1 vd 6..0=0x57 -vfncvt.rod.f.f.w 31..26=0x12 vm vs2 19..15=0x15 14..12=0x1 vd 6..0=0x57 -vfncvt.rtz.xu.f.w 31..26=0x12 vm vs2 19..15=0x16 14..12=0x1 vd 6..0=0x57 -vfncvt.rtz.x.f.w 31..26=0x12 vm vs2 19..15=0x17 14..12=0x1 vd 6..0=0x57 - -vfsqrt.v 31..26=0x13 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57 -vfrsqrt7.v 31..26=0x13 vm vs2 19..15=0x04 14..12=0x1 vd 6..0=0x57 -vfrec7.v 31..26=0x13 vm vs2 19..15=0x05 14..12=0x1 vd 6..0=0x57 -vfclass.v 31..26=0x13 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57 - -vfwadd.vv 31..26=0x30 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwredusum.vs 31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwsub.vv 31..26=0x32 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwredosum.vs 31..26=0x33 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwadd.wv 31..26=0x34 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwsub.wv 31..26=0x36 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwmul.vv 31..26=0x38 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwmacc.vv 31..26=0x3c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwnmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwmsac.vv 31..26=0x3e vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwnmsac.vv 31..26=0x3f vm vs2 vs1 14..12=0x1 vd 6..0=0x57 - -# OPIVX -vadd.vx 31..26=0x00 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vsub.vx 31..26=0x02 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vrsub.vx 31..26=0x03 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vminu.vx 31..26=0x04 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmin.vx 31..26=0x05 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmaxu.vx 31..26=0x06 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmax.vx 31..26=0x07 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vand.vx 31..26=0x09 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vor.vx 31..26=0x0a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vxor.vx 31..26=0x0b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vrgather.vx 31..26=0x0c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vslideup.vx 31..26=0x0e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vslidedown.vx 31..26=0x0f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 - -vadc.vxm 31..26=0x10 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmadc.vxm 31..26=0x11 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmadc.vx 31..26=0x11 25=1 vs2 rs1 14..12=0x4 vd 6..0=0x57 -vsbc.vxm 31..26=0x12 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmsbc.vxm 31..26=0x13 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmsbc.vx 31..26=0x13 25=1 vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmerge.vxm 31..26=0x17 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmv.v.x 31..26=0x17 25=1 24..20=0 rs1 14..12=0x4 vd 6..0=0x57 -vmseq.vx 31..26=0x18 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmsne.vx 31..26=0x19 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmsltu.vx 31..26=0x1a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmslt.vx 31..26=0x1b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmsleu.vx 31..26=0x1c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmsle.vx 31..26=0x1d vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmsgtu.vx 31..26=0x1e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmsgt.vx 31..26=0x1f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 - -vsaddu.vx 31..26=0x20 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vsadd.vx 31..26=0x21 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vssubu.vx 31..26=0x22 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vssub.vx 31..26=0x23 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vsll.vx 31..26=0x25 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vsmul.vx 31..26=0x27 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vsrl.vx 31..26=0x28 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vsra.vx 31..26=0x29 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vssrl.vx 31..26=0x2a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vssra.vx 31..26=0x2b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vnsrl.wx 31..26=0x2c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vnsra.wx 31..26=0x2d vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vnclipu.wx 31..26=0x2e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vnclip.wx 31..26=0x2f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 - -# OPIVV -vadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vsub.vv 31..26=0x02 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vminu.vv 31..26=0x04 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmin.vv 31..26=0x05 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmaxu.vv 31..26=0x06 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmax.vv 31..26=0x07 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vand.vv 31..26=0x09 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vor.vv 31..26=0x0a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vxor.vv 31..26=0x0b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vrgather.vv 31..26=0x0c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vrgatherei16.vv 31..26=0x0e vm vs2 vs1 14..12=0x0 vd 6..0=0x57 - -vadc.vvm 31..26=0x10 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmadc.vvm 31..26=0x11 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmadc.vv 31..26=0x11 25=1 vs2 vs1 14..12=0x0 vd 6..0=0x57 -vsbc.vvm 31..26=0x12 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmsbc.vvm 31..26=0x13 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmsbc.vv 31..26=0x13 25=1 vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmerge.vvm 31..26=0x17 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmv.v.v 31..26=0x17 25=1 24..20=0 vs1 14..12=0x0 vd 6..0=0x57 -vmseq.vv 31..26=0x18 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmsne.vv 31..26=0x19 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmsltu.vv 31..26=0x1a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmslt.vv 31..26=0x1b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmsleu.vv 31..26=0x1c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmsle.vv 31..26=0x1d vm vs2 vs1 14..12=0x0 vd 6..0=0x57 - -vsaddu.vv 31..26=0x20 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vsadd.vv 31..26=0x21 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vssubu.vv 31..26=0x22 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vssub.vv 31..26=0x23 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vsll.vv 31..26=0x25 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vsmul.vv 31..26=0x27 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vsrl.vv 31..26=0x28 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vsra.vv 31..26=0x29 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vssrl.vv 31..26=0x2a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vssra.vv 31..26=0x2b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vnsrl.wv 31..26=0x2c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vnsra.wv 31..26=0x2d vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vnclipu.wv 31..26=0x2e vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vnclip.wv 31..26=0x2f vm vs2 vs1 14..12=0x0 vd 6..0=0x57 - -vwredsumu.vs 31..26=0x30 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 - -# OPIVI -vadd.vi 31..26=0x00 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vrsub.vi 31..26=0x03 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vand.vi 31..26=0x09 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vor.vi 31..26=0x0a vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vxor.vi 31..26=0x0b vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vrgather.vi 31..26=0x0c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vslideup.vi 31..26=0x0e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vslidedown.vi 31..26=0x0f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 - -vadc.vim 31..26=0x10 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmadc.vim 31..26=0x11 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmadc.vi 31..26=0x11 25=1 vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmerge.vim 31..26=0x17 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmv.v.i 31..26=0x17 25=1 24..20=0 simm5 14..12=0x3 vd 6..0=0x57 -vmseq.vi 31..26=0x18 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmsne.vi 31..26=0x19 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmsleu.vi 31..26=0x1c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmsle.vi 31..26=0x1d vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmsgtu.vi 31..26=0x1e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmsgt.vi 31..26=0x1f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 - -vsaddu.vi 31..26=0x20 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vsadd.vi 31..26=0x21 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vsll.vi 31..26=0x25 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmv1r.v 31..26=0x27 25=1 vs2 19..15=0 14..12=0x3 vd 6..0=0x57 -vmv2r.v 31..26=0x27 25=1 vs2 19..15=1 14..12=0x3 vd 6..0=0x57 -vmv4r.v 31..26=0x27 25=1 vs2 19..15=3 14..12=0x3 vd 6..0=0x57 -vmv8r.v 31..26=0x27 25=1 vs2 19..15=7 14..12=0x3 vd 6..0=0x57 -vsrl.vi 31..26=0x28 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vsra.vi 31..26=0x29 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vssrl.vi 31..26=0x2a vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vssra.vi 31..26=0x2b vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vnsrl.wi 31..26=0x2c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vnsra.wi 31..26=0x2d vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vnclipu.wi 31..26=0x2e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vnclip.wi 31..26=0x2f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 - -# OPMVV -vredsum.vs 31..26=0x00 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vredand.vs 31..26=0x01 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vredor.vs 31..26=0x02 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vredxor.vs 31..26=0x03 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vredminu.vs 31..26=0x04 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vredmin.vs 31..26=0x05 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vredmaxu.vs 31..26=0x06 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vaaddu.vv 31..26=0x08 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vaadd.vv 31..26=0x09 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vasubu.vv 31..26=0x0a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vasub.vv 31..26=0x0b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 - -vmv.x.s 31..26=0x10 25=1 vs2 19..15=0 14..12=0x2 rd 6..0=0x57 - -# Vector Integer Extension Instructions -# https://github.com/riscv/riscv-v-spec/blob/e49574c92b072fd4d71e6cb20f7e8154de5b83fe/v-spec.adoc#123-vector-integer-extension -vzext.vf8 31..26=0x12 vm vs2 19..15=2 14..12=0x2 vd 6..0=0x57 -vsext.vf8 31..26=0x12 vm vs2 19..15=3 14..12=0x2 vd 6..0=0x57 -vzext.vf4 31..26=0x12 vm vs2 19..15=4 14..12=0x2 vd 6..0=0x57 -vsext.vf4 31..26=0x12 vm vs2 19..15=5 14..12=0x2 vd 6..0=0x57 -vzext.vf2 31..26=0x12 vm vs2 19..15=6 14..12=0x2 vd 6..0=0x57 -vsext.vf2 31..26=0x12 vm vs2 19..15=7 14..12=0x2 vd 6..0=0x57 - -vcompress.vm 31..26=0x17 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmandn.mm 31..26=0x18 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmand.mm 31..26=0x19 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmor.mm 31..26=0x1a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmxor.mm 31..26=0x1b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmorn.mm 31..26=0x1c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmnand.mm 31..26=0x1d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmnor.mm 31..26=0x1e vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmxnor.mm 31..26=0x1f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 - -vmsbf.m 31..26=0x14 vm vs2 19..15=0x01 14..12=0x2 vd 6..0=0x57 -vmsof.m 31..26=0x14 vm vs2 19..15=0x02 14..12=0x2 vd 6..0=0x57 -vmsif.m 31..26=0x14 vm vs2 19..15=0x03 14..12=0x2 vd 6..0=0x57 -viota.m 31..26=0x14 vm vs2 19..15=0x10 14..12=0x2 vd 6..0=0x57 -vid.v 31..26=0x14 vm 24..20=0 19..15=0x11 14..12=0x2 vd 6..0=0x57 -vcpop.m 31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57 -vfirst.m 31..26=0x10 vm vs2 19..15=0x11 14..12=0x2 rd 6..0=0x57 - -vdivu.vv 31..26=0x20 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vdiv.vv 31..26=0x21 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vremu.vv 31..26=0x22 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vrem.vv 31..26=0x23 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmulhu.vv 31..26=0x24 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmul.vv 31..26=0x25 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmulhsu.vv 31..26=0x26 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmulh.vv 31..26=0x27 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmadd.vv 31..26=0x29 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vnmsub.vv 31..26=0x2b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmacc.vv 31..26=0x2d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vnmsac.vv 31..26=0x2f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 - -vwaddu.vv 31..26=0x30 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwadd.vv 31..26=0x31 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwsubu.vv 31..26=0x32 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwsub.vv 31..26=0x33 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwaddu.wv 31..26=0x34 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwadd.wv 31..26=0x35 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwsubu.wv 31..26=0x36 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwsub.wv 31..26=0x37 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwmulu.vv 31..26=0x38 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwmulsu.vv 31..26=0x3a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwmul.vv 31..26=0x3b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwmaccu.vv 31..26=0x3c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwmaccsu.vv 31..26=0x3f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 - -# OPMVX -vaaddu.vx 31..26=0x08 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vaadd.vx 31..26=0x09 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vasubu.vx 31..26=0x0a vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vasub.vx 31..26=0x0b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 - -vmv.s.x 31..26=0x10 25=1 24..20=0 rs1 14..12=0x6 vd 6..0=0x57 -vslide1up.vx 31..26=0x0e vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vslide1down.vx 31..26=0x0f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 - -vdivu.vx 31..26=0x20 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vdiv.vx 31..26=0x21 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vremu.vx 31..26=0x22 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vrem.vx 31..26=0x23 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vmulhu.vx 31..26=0x24 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vmul.vx 31..26=0x25 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vmulhsu.vx 31..26=0x26 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vmulh.vx 31..26=0x27 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vmadd.vx 31..26=0x29 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vnmsub.vx 31..26=0x2b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vmacc.vx 31..26=0x2d vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vnmsac.vx 31..26=0x2f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 - -vwaddu.vx 31..26=0x30 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwadd.vx 31..26=0x31 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwsubu.vx 31..26=0x32 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwsub.vx 31..26=0x33 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwaddu.wx 31..26=0x34 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwadd.wx 31..26=0x35 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwsubu.wx 31..26=0x36 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwsub.wx 31..26=0x37 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwmulu.vx 31..26=0x38 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwmulsu.vx 31..26=0x3a vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwmul.vx 31..26=0x3b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwmaccu.vx 31..26=0x3c vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwmacc.vx 31..26=0x3d vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwmaccus.vx 31..26=0x3e vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwmaccsu.vx 31..26=0x3f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 - -# Zvamo -vamoswapei8.v 31..27=0x01 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f -vamoaddei8.v 31..27=0x00 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f -vamoxorei8.v 31..27=0x04 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f -vamoandei8.v 31..27=0x0c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f -vamoorei8.v 31..27=0x08 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f -vamominei8.v 31..27=0x10 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f -vamomaxei8.v 31..27=0x14 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f -vamominuei8.v 31..27=0x18 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f -vamomaxuei8.v 31..27=0x1c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f - -vamoswapei16.v 31..27=0x01 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f -vamoaddei16.v 31..27=0x00 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f -vamoxorei16.v 31..27=0x04 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f -vamoandei16.v 31..27=0x0c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f -vamoorei16.v 31..27=0x08 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f -vamominei16.v 31..27=0x10 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f -vamomaxei16.v 31..27=0x14 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f -vamominuei16.v 31..27=0x18 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f -vamomaxuei16.v 31..27=0x1c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f - -vamoswapei32.v 31..27=0x01 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f -vamoaddei32.v 31..27=0x00 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f -vamoxorei32.v 31..27=0x04 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f -vamoandei32.v 31..27=0x0c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f -vamoorei32.v 31..27=0x08 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f -vamominei32.v 31..27=0x10 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f -vamomaxei32.v 31..27=0x14 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f -vamominuei32.v 31..27=0x18 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f -vamomaxuei32.v 31..27=0x1c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f - -vamoswapei64.v 31..27=0x01 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f -vamoaddei64.v 31..27=0x00 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f -vamoxorei64.v 31..27=0x04 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f -vamoandei64.v 31..27=0x0c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f -vamoorei64.v 31..27=0x08 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f -vamominei64.v 31..27=0x10 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f -vamomaxei64.v 31..27=0x14 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f -vamominuei64.v 31..27=0x18 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f -vamomaxuei64.v 31..27=0x1c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f diff --git a/rv_v b/rv_v new file mode 100644 index 0000000..29a0ff8 --- /dev/null +++ b/rv_v @@ -0,0 +1,528 @@ +# format of a line in this file: +# +# +# is given by specifying one or more range/value pairs: +# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) +# +# is one of vd, vs3, vs1, vs2, vm, nf, wd, simm5, zimm10, zimm11 + +# configuration setting +# https://github.com/riscv/riscv-v-spec/blob/master/vcfg-format.adoc +vsetivli 31=1 30=1 zimm10 zimm 14..12=0x7 rd 6..0=0x57 +vsetvli 31=0 zimm11 rs1 14..12=0x7 rd 6..0=0x57 +vsetvl 31=1 30..25=0x0 rs2 rs1 14..12=0x7 rd 6..0=0x57 + +# +# Vector Loads and Store +# https://github.com/riscv/riscv-v-spec/blob/master/vmem-format.adoc +# +# Vector Unit-Stride Instructions (including segment part) +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#74-vector-unit-stride-instructions +vlm.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vd 6..0=0x07 +vsm.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vs3 6..0=0x27 +vle8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07 +vle16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07 +vle32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07 +vle64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07 +vle128.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07 +vle256.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07 +vle512.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07 +vle1024.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07 +vse8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27 +vse16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27 +vse32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27 +vse64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27 +vse128.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27 +vse256.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27 +vse512.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27 +vse1024.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27 + +# Vector Indexed-Unordered Instructions (including segment part) +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#76-vector-indexed-instructions +vluxei8.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 +vluxei16.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 +vluxei32.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 +vluxei64.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 +vluxei128.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 +vluxei256.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 +vluxei512.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 +vluxei1024.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 +vsuxei8.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 +vsuxei16.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 +vsuxei32.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 +vsuxei64.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 +vsuxei128.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 +vsuxei256.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 +vsuxei512.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 +vsuxei1024.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 + +# Vector Strided Instructions (including segment part) +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#75-vector-strided-instructions +vlse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07 +vlse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07 +vlse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07 +vlse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07 +vlse128.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07 +vlse256.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07 +vlse512.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07 +vlse1024.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07 +vsse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27 +vsse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27 +vsse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27 +vsse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27 +vsse128.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27 +vsse256.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27 +vsse512.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27 +vsse1024.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27 + +# Vector Indexed-Ordered Instructions (including segment part) +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#76-vector-indexed-instructions +vloxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 +vloxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 +vloxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 +vloxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 +vloxei128.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 +vloxei256.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 +vloxei512.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 +vloxei1024.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 +vsoxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 +vsoxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 +vsoxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 +vsoxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 +vsoxei128.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 +vsoxei256.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 +vsoxei512.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 +vsoxei1024.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 + +# Unit-stride F31..29=0ault-Only-First Loads +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#77-unit-stride-fault-only-first-loads +vle8ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07 +vle16ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07 +vle32ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07 +vle64ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07 +vle128ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07 +vle256ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07 +vle512ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07 +vle1024ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07 + +# Vector Load/Store Whole Registers +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#79-vector-loadstore-whole-register-instructions +vl1re8.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +vl1re16.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +vl1re32.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +vl1re64.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +vl2re8.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +vl2re16.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +vl2re32.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +vl2re64.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +vl4re8.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +vl4re16.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +vl4re32.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +vl4re64.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +vl8re8.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +vl8re16.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +vl8re32.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +vl8re64.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +vs1r.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 +vs2r.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 +vs4r.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 +vs8r.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 + +# Vector Floating-Point Instructions +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#14-vector-floating-point-instructions +# OPFVF +vfadd.vf 31..26=0x00 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfsub.vf 31..26=0x02 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmin.vf 31..26=0x04 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmax.vf 31..26=0x06 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfsgnj.vf 31..26=0x08 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfsgnjn.vf 31..26=0x09 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfsgnjx.vf 31..26=0x0a vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfslide1up.vf 31..26=0x0e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfslide1down.vf 31..26=0x0f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmv.s.f 31..26=0x10 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57 + +vfmerge.vfm 31..26=0x17 25=0 vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmv.v.f 31..26=0x17 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57 +vmfeq.vf 31..26=0x18 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vmfle.vf 31..26=0x19 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vmflt.vf 31..26=0x1b vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vmfne.vf 31..26=0x1c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vmfgt.vf 31..26=0x1d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vmfge.vf 31..26=0x1f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 + +vfdiv.vf 31..26=0x20 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfrdiv.vf 31..26=0x21 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmul.vf 31..26=0x24 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfrsub.vf 31..26=0x27 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmadd.vf 31..26=0x28 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfnmadd.vf 31..26=0x29 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmsub.vf 31..26=0x2a vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfnmsub.vf 31..26=0x2b vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmacc.vf 31..26=0x2c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfnmacc.vf 31..26=0x2d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmsac.vf 31..26=0x2e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfnmsac.vf 31..26=0x2f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 + +vfwadd.vf 31..26=0x30 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwsub.vf 31..26=0x32 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwadd.wf 31..26=0x34 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwsub.wf 31..26=0x36 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwmul.vf 31..26=0x38 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwmacc.vf 31..26=0x3c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwnmacc.vf 31..26=0x3d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwmsac.vf 31..26=0x3e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwnmsac.vf 31..26=0x3f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 + +# OPFVV +vfadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfredusum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfsub.vv 31..26=0x02 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfredosum.vs 31..26=0x03 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmin.vv 31..26=0x04 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfredmin.vs 31..26=0x05 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmax.vv 31..26=0x06 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfsgnj.vv 31..26=0x08 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfsgnjn.vv 31..26=0x09 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfsgnjx.vv 31..26=0x0a vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmv.f.s 31..26=0x10 25=1 vs2 19..15=0 14..12=0x1 rd 6..0=0x57 + +vmfeq.vv 31..26=0x18 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vmfle.vv 31..26=0x19 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vmflt.vv 31..26=0x1b vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vmfne.vv 31..26=0x1c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 + +vfdiv.vv 31..26=0x20 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmul.vv 31..26=0x24 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmadd.vv 31..26=0x28 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfnmadd.vv 31..26=0x29 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmsub.vv 31..26=0x2a vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfnmsub.vv 31..26=0x2b vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmacc.vv 31..26=0x2c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfnmacc.vv 31..26=0x2d vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmsac.vv 31..26=0x2e vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfnmsac.vv 31..26=0x2f vm vs2 vs1 14..12=0x1 vd 6..0=0x57 + +vfcvt.xu.f.v 31..26=0x12 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57 +vfcvt.x.f.v 31..26=0x12 vm vs2 19..15=0x01 14..12=0x1 vd 6..0=0x57 +vfcvt.f.xu.v 31..26=0x12 vm vs2 19..15=0x02 14..12=0x1 vd 6..0=0x57 +vfcvt.f.x.v 31..26=0x12 vm vs2 19..15=0x03 14..12=0x1 vd 6..0=0x57 +vfcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x06 14..12=0x1 vd 6..0=0x57 +vfcvt.rtz.x.f.v 31..26=0x12 vm vs2 19..15=0x07 14..12=0x1 vd 6..0=0x57 + +vfwcvt.xu.f.v 31..26=0x12 vm vs2 19..15=0x08 14..12=0x1 vd 6..0=0x57 +vfwcvt.x.f.v 31..26=0x12 vm vs2 19..15=0x09 14..12=0x1 vd 6..0=0x57 +vfwcvt.f.xu.v 31..26=0x12 vm vs2 19..15=0x0A 14..12=0x1 vd 6..0=0x57 +vfwcvt.f.x.v 31..26=0x12 vm vs2 19..15=0x0B 14..12=0x1 vd 6..0=0x57 +vfwcvt.f.f.v 31..26=0x12 vm vs2 19..15=0x0C 14..12=0x1 vd 6..0=0x57 +vfwcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x0E 14..12=0x1 vd 6..0=0x57 +vfwcvt.rtz.x.f.v 31..26=0x12 vm vs2 19..15=0x0F 14..12=0x1 vd 6..0=0x57 + +vfncvt.xu.f.w 31..26=0x12 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57 +vfncvt.x.f.w 31..26=0x12 vm vs2 19..15=0x11 14..12=0x1 vd 6..0=0x57 +vfncvt.f.xu.w 31..26=0x12 vm vs2 19..15=0x12 14..12=0x1 vd 6..0=0x57 +vfncvt.f.x.w 31..26=0x12 vm vs2 19..15=0x13 14..12=0x1 vd 6..0=0x57 +vfncvt.f.f.w 31..26=0x12 vm vs2 19..15=0x14 14..12=0x1 vd 6..0=0x57 +vfncvt.rod.f.f.w 31..26=0x12 vm vs2 19..15=0x15 14..12=0x1 vd 6..0=0x57 +vfncvt.rtz.xu.f.w 31..26=0x12 vm vs2 19..15=0x16 14..12=0x1 vd 6..0=0x57 +vfncvt.rtz.x.f.w 31..26=0x12 vm vs2 19..15=0x17 14..12=0x1 vd 6..0=0x57 + +vfsqrt.v 31..26=0x13 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57 +vfrsqrt7.v 31..26=0x13 vm vs2 19..15=0x04 14..12=0x1 vd 6..0=0x57 +vfrec7.v 31..26=0x13 vm vs2 19..15=0x05 14..12=0x1 vd 6..0=0x57 +vfclass.v 31..26=0x13 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57 + +vfwadd.vv 31..26=0x30 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwredusum.vs 31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwsub.vv 31..26=0x32 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwredosum.vs 31..26=0x33 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwadd.wv 31..26=0x34 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwsub.wv 31..26=0x36 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwmul.vv 31..26=0x38 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwmacc.vv 31..26=0x3c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwnmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwmsac.vv 31..26=0x3e vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwnmsac.vv 31..26=0x3f vm vs2 vs1 14..12=0x1 vd 6..0=0x57 + +# OPIVX +vadd.vx 31..26=0x00 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsub.vx 31..26=0x02 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vrsub.vx 31..26=0x03 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vminu.vx 31..26=0x04 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmin.vx 31..26=0x05 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmaxu.vx 31..26=0x06 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmax.vx 31..26=0x07 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vand.vx 31..26=0x09 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vor.vx 31..26=0x0a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vxor.vx 31..26=0x0b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vrgather.vx 31..26=0x0c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vslideup.vx 31..26=0x0e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vslidedown.vx 31..26=0x0f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 + +vadc.vxm 31..26=0x10 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmadc.vxm 31..26=0x11 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmadc.vx 31..26=0x11 25=1 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsbc.vxm 31..26=0x12 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsbc.vxm 31..26=0x13 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsbc.vx 31..26=0x13 25=1 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmerge.vxm 31..26=0x17 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmv.v.x 31..26=0x17 25=1 24..20=0 rs1 14..12=0x4 vd 6..0=0x57 +vmseq.vx 31..26=0x18 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsne.vx 31..26=0x19 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsltu.vx 31..26=0x1a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmslt.vx 31..26=0x1b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsleu.vx 31..26=0x1c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsle.vx 31..26=0x1d vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsgtu.vx 31..26=0x1e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsgt.vx 31..26=0x1f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 + +vsaddu.vx 31..26=0x20 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsadd.vx 31..26=0x21 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vssubu.vx 31..26=0x22 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vssub.vx 31..26=0x23 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsll.vx 31..26=0x25 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsmul.vx 31..26=0x27 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsrl.vx 31..26=0x28 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsra.vx 31..26=0x29 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vssrl.vx 31..26=0x2a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vssra.vx 31..26=0x2b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vnsrl.wx 31..26=0x2c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vnsra.wx 31..26=0x2d vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vnclipu.wx 31..26=0x2e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vnclip.wx 31..26=0x2f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 + +# OPIVV +vadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsub.vv 31..26=0x02 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vminu.vv 31..26=0x04 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmin.vv 31..26=0x05 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmaxu.vv 31..26=0x06 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmax.vv 31..26=0x07 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vand.vv 31..26=0x09 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vor.vv 31..26=0x0a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vxor.vv 31..26=0x0b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vrgather.vv 31..26=0x0c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vrgatherei16.vv 31..26=0x0e vm vs2 vs1 14..12=0x0 vd 6..0=0x57 + +vadc.vvm 31..26=0x10 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmadc.vvm 31..26=0x11 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmadc.vv 31..26=0x11 25=1 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsbc.vvm 31..26=0x12 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsbc.vvm 31..26=0x13 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsbc.vv 31..26=0x13 25=1 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmerge.vvm 31..26=0x17 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmv.v.v 31..26=0x17 25=1 24..20=0 vs1 14..12=0x0 vd 6..0=0x57 +vmseq.vv 31..26=0x18 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsne.vv 31..26=0x19 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsltu.vv 31..26=0x1a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmslt.vv 31..26=0x1b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsleu.vv 31..26=0x1c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsle.vv 31..26=0x1d vm vs2 vs1 14..12=0x0 vd 6..0=0x57 + +vsaddu.vv 31..26=0x20 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsadd.vv 31..26=0x21 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vssubu.vv 31..26=0x22 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vssub.vv 31..26=0x23 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsll.vv 31..26=0x25 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsmul.vv 31..26=0x27 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsrl.vv 31..26=0x28 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsra.vv 31..26=0x29 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vssrl.vv 31..26=0x2a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vssra.vv 31..26=0x2b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vnsrl.wv 31..26=0x2c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vnsra.wv 31..26=0x2d vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vnclipu.wv 31..26=0x2e vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vnclip.wv 31..26=0x2f vm vs2 vs1 14..12=0x0 vd 6..0=0x57 + +vwredsumu.vs 31..26=0x30 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 + +# OPIVI +vadd.vi 31..26=0x00 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vrsub.vi 31..26=0x03 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vand.vi 31..26=0x09 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vor.vi 31..26=0x0a vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vxor.vi 31..26=0x0b vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vrgather.vi 31..26=0x0c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vslideup.vi 31..26=0x0e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vslidedown.vi 31..26=0x0f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 + +vadc.vim 31..26=0x10 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmadc.vim 31..26=0x11 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmadc.vi 31..26=0x11 25=1 vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmerge.vim 31..26=0x17 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmv.v.i 31..26=0x17 25=1 24..20=0 simm5 14..12=0x3 vd 6..0=0x57 +vmseq.vi 31..26=0x18 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmsne.vi 31..26=0x19 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmsleu.vi 31..26=0x1c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmsle.vi 31..26=0x1d vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmsgtu.vi 31..26=0x1e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmsgt.vi 31..26=0x1f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 + +vsaddu.vi 31..26=0x20 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vsadd.vi 31..26=0x21 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vsll.vi 31..26=0x25 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmv1r.v 31..26=0x27 25=1 vs2 19..15=0 14..12=0x3 vd 6..0=0x57 +vmv2r.v 31..26=0x27 25=1 vs2 19..15=1 14..12=0x3 vd 6..0=0x57 +vmv4r.v 31..26=0x27 25=1 vs2 19..15=3 14..12=0x3 vd 6..0=0x57 +vmv8r.v 31..26=0x27 25=1 vs2 19..15=7 14..12=0x3 vd 6..0=0x57 +vsrl.vi 31..26=0x28 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vsra.vi 31..26=0x29 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vssrl.vi 31..26=0x2a vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vssra.vi 31..26=0x2b vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vnsrl.wi 31..26=0x2c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vnsra.wi 31..26=0x2d vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vnclipu.wi 31..26=0x2e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vnclip.wi 31..26=0x2f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 + +# OPMVV +vredsum.vs 31..26=0x00 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredand.vs 31..26=0x01 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredor.vs 31..26=0x02 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredxor.vs 31..26=0x03 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredminu.vs 31..26=0x04 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredmin.vs 31..26=0x05 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredmaxu.vs 31..26=0x06 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vaaddu.vv 31..26=0x08 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vaadd.vv 31..26=0x09 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vasubu.vv 31..26=0x0a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vasub.vv 31..26=0x0b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 + +vmv.x.s 31..26=0x10 25=1 vs2 19..15=0 14..12=0x2 rd 6..0=0x57 + +# Vector Integer Extension Instructions +# https://github.com/riscv/riscv-v-spec/blob/e49574c92b072fd4d71e6cb20f7e8154de5b83fe/v-spec.adoc#123-vector-integer-extension +vzext.vf8 31..26=0x12 vm vs2 19..15=2 14..12=0x2 vd 6..0=0x57 +vsext.vf8 31..26=0x12 vm vs2 19..15=3 14..12=0x2 vd 6..0=0x57 +vzext.vf4 31..26=0x12 vm vs2 19..15=4 14..12=0x2 vd 6..0=0x57 +vsext.vf4 31..26=0x12 vm vs2 19..15=5 14..12=0x2 vd 6..0=0x57 +vzext.vf2 31..26=0x12 vm vs2 19..15=6 14..12=0x2 vd 6..0=0x57 +vsext.vf2 31..26=0x12 vm vs2 19..15=7 14..12=0x2 vd 6..0=0x57 + +vcompress.vm 31..26=0x17 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmandn.mm 31..26=0x18 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmand.mm 31..26=0x19 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmor.mm 31..26=0x1a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmxor.mm 31..26=0x1b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmorn.mm 31..26=0x1c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmnand.mm 31..26=0x1d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmnor.mm 31..26=0x1e vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmxnor.mm 31..26=0x1f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 + +vmsbf.m 31..26=0x14 vm vs2 19..15=0x01 14..12=0x2 vd 6..0=0x57 +vmsof.m 31..26=0x14 vm vs2 19..15=0x02 14..12=0x2 vd 6..0=0x57 +vmsif.m 31..26=0x14 vm vs2 19..15=0x03 14..12=0x2 vd 6..0=0x57 +viota.m 31..26=0x14 vm vs2 19..15=0x10 14..12=0x2 vd 6..0=0x57 +vid.v 31..26=0x14 vm 24..20=0 19..15=0x11 14..12=0x2 vd 6..0=0x57 +vcpop.m 31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57 +vfirst.m 31..26=0x10 vm vs2 19..15=0x11 14..12=0x2 rd 6..0=0x57 + +vdivu.vv 31..26=0x20 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vdiv.vv 31..26=0x21 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vremu.vv 31..26=0x22 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vrem.vv 31..26=0x23 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmulhu.vv 31..26=0x24 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmul.vv 31..26=0x25 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmulhsu.vv 31..26=0x26 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmulh.vv 31..26=0x27 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmadd.vv 31..26=0x29 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vnmsub.vv 31..26=0x2b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmacc.vv 31..26=0x2d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vnmsac.vv 31..26=0x2f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 + +vwaddu.vv 31..26=0x30 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwadd.vv 31..26=0x31 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwsubu.vv 31..26=0x32 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwsub.vv 31..26=0x33 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwaddu.wv 31..26=0x34 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwadd.wv 31..26=0x35 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwsubu.wv 31..26=0x36 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwsub.wv 31..26=0x37 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwmulu.vv 31..26=0x38 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwmulsu.vv 31..26=0x3a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwmul.vv 31..26=0x3b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwmaccu.vv 31..26=0x3c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwmaccsu.vv 31..26=0x3f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 + +# OPMVX +vaaddu.vx 31..26=0x08 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vaadd.vx 31..26=0x09 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vasubu.vx 31..26=0x0a vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vasub.vx 31..26=0x0b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 + +vmv.s.x 31..26=0x10 25=1 24..20=0 rs1 14..12=0x6 vd 6..0=0x57 +vslide1up.vx 31..26=0x0e vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vslide1down.vx 31..26=0x0f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 + +vdivu.vx 31..26=0x20 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vdiv.vx 31..26=0x21 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vremu.vx 31..26=0x22 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vrem.vx 31..26=0x23 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vmulhu.vx 31..26=0x24 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vmul.vx 31..26=0x25 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vmulhsu.vx 31..26=0x26 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vmulh.vx 31..26=0x27 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vmadd.vx 31..26=0x29 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vnmsub.vx 31..26=0x2b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vmacc.vx 31..26=0x2d vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vnmsac.vx 31..26=0x2f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 + +vwaddu.vx 31..26=0x30 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwadd.vx 31..26=0x31 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwsubu.vx 31..26=0x32 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwsub.vx 31..26=0x33 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwaddu.wx 31..26=0x34 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwadd.wx 31..26=0x35 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwsubu.wx 31..26=0x36 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwsub.wx 31..26=0x37 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmulu.vx 31..26=0x38 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmulsu.vx 31..26=0x3a vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmul.vx 31..26=0x3b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmaccu.vx 31..26=0x3c vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmacc.vx 31..26=0x3d vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmaccus.vx 31..26=0x3e vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmaccsu.vx 31..26=0x3f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 + +# Zvamo +vamoswapei8.v 31..27=0x01 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +vamoaddei8.v 31..27=0x00 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +vamoxorei8.v 31..27=0x04 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +vamoandei8.v 31..27=0x0c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +vamoorei8.v 31..27=0x08 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +vamominei8.v 31..27=0x10 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +vamomaxei8.v 31..27=0x14 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +vamominuei8.v 31..27=0x18 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +vamomaxuei8.v 31..27=0x1c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f + +vamoswapei16.v 31..27=0x01 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +vamoaddei16.v 31..27=0x00 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +vamoxorei16.v 31..27=0x04 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +vamoandei16.v 31..27=0x0c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +vamoorei16.v 31..27=0x08 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +vamominei16.v 31..27=0x10 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +vamomaxei16.v 31..27=0x14 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +vamominuei16.v 31..27=0x18 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +vamomaxuei16.v 31..27=0x1c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f + +vamoswapei32.v 31..27=0x01 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +vamoaddei32.v 31..27=0x00 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +vamoxorei32.v 31..27=0x04 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +vamoandei32.v 31..27=0x0c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +vamoorei32.v 31..27=0x08 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +vamominei32.v 31..27=0x10 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +vamomaxei32.v 31..27=0x14 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +vamominuei32.v 31..27=0x18 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +vamomaxuei32.v 31..27=0x1c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f + +vamoswapei64.v 31..27=0x01 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +vamoaddei64.v 31..27=0x00 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +vamoxorei64.v 31..27=0x04 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +vamoandei64.v 31..27=0x0c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +vamoorei64.v 31..27=0x08 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +vamominei64.v 31..27=0x10 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +vamomaxei64.v 31..27=0x14 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +vamominuei64.v 31..27=0x18 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +vamomaxuei64.v 31..27=0x1c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f -- cgit v1.1 From 925870f2f7c2329cc083f48fabe454b15e7817cb Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 18:36:23 +0530 Subject: migrate P-extension and its sub-extension opcodes - includes zbp and zbpbo sub extensions as well --- opcodes-rvp | 326 ---------------------------------------------------- unratified/rv32_p | 3 + unratified/rv64_p | 81 +++++++++++++ unratified/rv_p | 245 +++++++++++++++++++++++++++++++++++++++ unratified/rv_zbp | 15 +++ unratified/rv_zbpbo | 6 + 6 files changed, 350 insertions(+), 326 deletions(-) delete mode 100644 opcodes-rvp create mode 100644 unratified/rv32_p create mode 100644 unratified/rv64_p create mode 100644 unratified/rv_p create mode 100644 unratified/rv_zbp create mode 100644 unratified/rv_zbpbo diff --git a/opcodes-rvp b/opcodes-rvp deleted file mode 100644 index 4cb8a68..0000000 --- a/opcodes-rvp +++ /dev/null @@ -1,326 +0,0 @@ -add8 31..25=0b0100100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -add16 31..25=0b0100000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -add64 31..25=0b1100000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ave 31..25=0b1110000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -bitrev 31..25=0b1110011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -bitrevi 31..26=0b111010 imm6 rs1 14..12=0b000 rd 6..0=0b1110111 -bpick rs3 26..25=0b00 rs2 rs1 14..12=0b011 rd 6..0=0b1110111 -clrs8 31..25=0b1010111 24..20=0b00000 rs1 14..12=0b000 rd 6..0=0b1110111 -clrs16 31..25=0b1010111 24..20=0b01000 rs1 14..12=0b000 rd 6..0=0b1110111 -clrs32 31..25=0b1010111 24..20=0b11000 rs1 14..12=0b000 rd 6..0=0b1110111 -clo8 31..25=0b1010111 24..20=0b00011 rs1 14..12=0b000 rd 6..0=0b1110111 -clo16 31..25=0b1010111 24..20=0b01011 rs1 14..12=0b000 rd 6..0=0b1110111 -clo32 31..25=0b1010111 24..20=0b11011 rs1 14..12=0b000 rd 6..0=0b1110111 -clz8 31..25=0b1010111 24..20=0b00001 rs1 14..12=0b000 rd 6..0=0b1110111 -clz16 31..25=0b1010111 24..20=0b01001 rs1 14..12=0b000 rd 6..0=0b1110111 -clz32 31..25=0b1010111 24..20=0b11001 rs1 14..12=0b000 rd 6..0=0b1110111 -cmpeq8 31..25=0b0100111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -cmpeq16 31..25=0b0100110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -cras16 31..25=0b0100010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -crsa16 31..25=0b0100011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -insb 31..25=0b1010110 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -kabs8 31..25=0b1010110 24..20=0b10000 rs1 14..12=0b000 rd 6..0=0b1110111 -kabs16 31..25=0b1010110 24..20=0b10001 rs1 14..12=0b000 rd 6..0=0b1110111 -kabsw 31..25=0b1010110 24..20=0b10100 rs1 14..12=0b000 rd 6..0=0b1110111 -kadd8 31..25=0b0001100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kadd16 31..25=0b0001000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kadd64 31..25=0b1001000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kaddh 31..25=0b0000010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kaddw 31..25=0b0000000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kcras16 31..25=0b0001010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kcrsa16 31..25=0b0001011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kdmbb 31..25=0b0000101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmbt 31..25=0b0001101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmtt 31..25=0b0010101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmabb 31..25=0b1101001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmabt 31..25=0b1110001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmatt 31..25=0b1111001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -khm8 31..25=0b1000111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -khmx8 31..25=0b1001111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -khm16 31..25=0b1000011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -khmx16 31..25=0b1001011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -khmbb 31..25=0b0000110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -khmbt 31..25=0b0001110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -khmtt 31..25=0b0010110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmabb 31..25=0b0101101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmabt 31..25=0b0110101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmatt 31..25=0b0111101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmada 31..25=0b0100100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmaxda 31..25=0b0100101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmads 31..25=0b0101110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmadrs 31..25=0b0110110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmaxds 31..25=0b0111110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmar64 31..25=0b1001010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmda 31..25=0b0011100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmxda 31..25=0b0011101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmac 31..25=0b0110000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmac.u 31..25=0b0111000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawb 31..25=0b0100011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawb.u 31..25=0b0101011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawb2 31..25=0b1100111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawb2.u 31..25=0b1101111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawt 31..25=0b0110011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawt.u 31..25=0b0111011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawt2 31..25=0b1110111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawt2.u 31..25=0b1111111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmsb 31..25=0b0100001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmsb.u 31..25=0b0101001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmwb2 31..25=0b1000111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmwb2.u 31..25=0b1001111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmwt2 31..25=0b1010111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmwt2.u 31..25=0b1011111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmsda 31..25=0b0100110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmsxda 31..25=0b0100111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmsr64 31..25=0b1001011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ksllw 31..25=0b0010011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kslliw 31..25=0b0011011 imm5 rs1 14..12=0b001 rd 6..0=0b1110111 -ksll8 31..25=0b0110110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kslli8 31..25=0b0111110 24..23=0b01 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -ksll16 31..25=0b0110010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kslli16 31..25=0b0111010 24=0b1 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -kslra8 31..25=0b0101111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kslra8.u 31..25=0b0110111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kslra16 31..25=0b0101011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kslra16.u 31..25=0b0110011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kslraw 31..25=0b0110111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kslraw.u 31..25=0b0111111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kstas16 31..25=0b1100010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kstsa16 31..25=0b1100011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ksub8 31..25=0b0001101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ksub16 31..25=0b0001001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ksub64 31..25=0b1001001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ksubh 31..25=0b0000011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ksubw 31..25=0b0000001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kwmmul 31..25=0b0110001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kwmmul.u 31..25=0b0111001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -maddr32 31..25=0b1100010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -maxw 31..25=0b1111001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -minw 31..25=0b1111000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -msubr32 31..25=0b1100011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -mulr64 31..25=0b1111000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -mulsr64 31..25=0b1110000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -pbsad 31..25=0b1111110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -pbsada 31..25=0b1111111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -pkbb16 31..25=0b0000111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -pkbt16 31..25=0b0001111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -pktt16 31..25=0b0010111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -pktb16 31..25=0b0011111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -radd8 31..25=0b0000100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -radd16 31..25=0b0000000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -radd64 31..25=0b1000000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -raddw 31..25=0b0010000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -rcras16 31..25=0b0000010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -rcrsa16 31..25=0b0000011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -rstas16 31..25=0b1011010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -rstsa16 31..25=0b1011011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -rsub8 31..25=0b0000101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -rsub16 31..25=0b0000001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -rsub64 31..25=0b1000001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -rsubw 31..25=0b0010001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -sclip8 31..25=0b1000110 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -sclip16 31..25=0b1000010 24=0b0 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -sclip32 31..25=0b1110010 imm5 rs1 14..12=0b000 rd 6..0=0b1110111 -scmple8 31..25=0b0001111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -scmple16 31..25=0b0001110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -scmplt8 31..25=0b0000111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -scmplt16 31..25=0b0000110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -sll8 31..25=0b0101110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -slli8 31..25=0b0111110 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -sll16 31..25=0b0101010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -slli16 31..25=0b0111010 24=0b0 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -smal 31..25=0b0101111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smalbb 31..25=0b1000100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smalbt 31..25=0b1001100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smaltt 31..25=0b1010100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smalda 31..25=0b1000110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smalxda 31..25=0b1001110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smalds 31..25=0b1000101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smaldrs 31..25=0b1001101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smalxds 31..25=0b1010101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smar64 31..25=0b1000010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smaqa 31..25=0b1100100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smaqa.su 31..25=0b1100101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smax8 31..25=0b1000101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smax16 31..25=0b1000001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smbb16 31..25=0b0000100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smbt16 31..25=0b0001100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smtt16 31..25=0b0010100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smds 31..25=0b0101100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smdrs 31..25=0b0110100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smxds 31..25=0b0111100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smin8 31..25=0b1000100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smin16 31..25=0b1000000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smmul 31..25=0b0100000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smmul.u 31..25=0b0101000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smmwb 31..25=0b0100010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smmwb.u 31..25=0b0101010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smmwt 31..25=0b0110010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smmwt.u 31..25=0b0111010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smslda 31..25=0b1010110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smslxda 31..25=0b1011110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smsr64 31..25=0b1000011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smul8 31..25=0b1010100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smulx8 31..25=0b1010101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smul16 31..25=0b1010000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smulx16 31..25=0b1010001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -sra.u 31..25=0b0010010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -srai.u 31..26=0b110101 imm6 rs1 14..12=0b001 rd 6..0=0b1110111 -sra8 31..25=0b0101100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -sra8.u 31..25=0b0110100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -srai8 31..25=0b0111100 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -srai8.u 31..25=0b0111100 24..23=0b01 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -sra16 31..25=0b0101000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -sra16.u 31..25=0b0110000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -srai16 31..25=0b0111000 24=0b0 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -srai16.u 31..25=0b0111000 24=0b1 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -srl8 31..25=0b0101101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -srl8.u 31..25=0b0110101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -srli8 31..25=0b0111101 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -srli8.u 31..25=0b0111101 24..23=0b01 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -srl16 31..25=0b0101001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -srl16.u 31..25=0b0110001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -srli16 31..25=0b0111001 24=0b0 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -srli16.u 31..25=0b0111001 24=0b1 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -stas16 31..25=0b1111010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -stsa16 31..25=0b1111011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -sub8 31..25=0b0100101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -sub16 31..25=0b0100001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -sub64 31..25=0b1100001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -sunpkd810 31..25=0b1010110 24..20=0b01000 rs1 14..12=0b000 rd 6..0=0b1110111 -sunpkd820 31..25=0b1010110 24..20=0b01001 rs1 14..12=0b000 rd 6..0=0b1110111 -sunpkd830 31..25=0b1010110 24..20=0b01010 rs1 14..12=0b000 rd 6..0=0b1110111 -sunpkd831 31..25=0b1010110 24..20=0b01011 rs1 14..12=0b000 rd 6..0=0b1110111 -sunpkd832 31..25=0b1010110 24..20=0b10011 rs1 14..12=0b000 rd 6..0=0b1110111 -swap8 31..25=0b1010110 24..20=0b11000 rs1 14..12=0b000 rd 6..0=0b1110111 -uclip8 31..25=0b1000110 24..23=0b10 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -uclip16 31..25=0b1000010 24=0b1 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -uclip32 31..25=0b1111010 imm5 rs1 14..12=0b000 rd 6..0=0b1110111 -ucmple8 31..25=0b0011111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ucmple16 31..25=0b0011110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ucmplt8 31..25=0b0010111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ucmplt16 31..25=0b0010110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ukadd8 31..25=0b0011100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ukadd16 31..25=0b0011000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ukadd64 31..25=0b1011000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ukaddh 31..25=0b0001010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ukaddw 31..25=0b0001000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ukcras16 31..25=0b0011010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ukcrsa16 31..25=0b0011011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ukmar64 31..25=0b1011010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ukmsr64 31..25=0b1011011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ukstas16 31..25=0b1110010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ukstsa16 31..25=0b1110011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -uksub8 31..25=0b0011101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -uksub16 31..25=0b0011001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -uksub64 31..25=0b1011001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -uksubh 31..25=0b0001011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -uksubw 31..25=0b0001001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -umar64 31..25=0b1010010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -umaqa 31..25=0b1100110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umax8 31..25=0b1001101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umax16 31..25=0b1001001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umin8 31..25=0b1001100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umin16 31..25=0b1001000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umsr64 31..25=0b1010011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -umul8 31..25=0b1011100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umulx8 31..25=0b1011101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umul16 31..25=0b1011000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umulx16 31..25=0b1011001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -uradd8 31..25=0b0010100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -uradd16 31..25=0b0010000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -uradd64 31..25=0b1010000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -uraddw 31..25=0b0011000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -urcras16 31..25=0b0010010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -urcrsa16 31..25=0b0010011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -urstas16 31..25=0b1101010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -urstsa16 31..25=0b1101011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ursub8 31..25=0b0010101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ursub16 31..25=0b0010001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ursub64 31..25=0b1010001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ursubw 31..25=0b0011001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -wexti 31..25=0b1101111 imm5 rs1 14..12=0b000 rd 6..0=0b1110111 -wext 31..25=0b1100111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -zunpkd810 31..25=0b1010110 24..20=0b01100 rs1 14..12=0b000 rd 6..0=0b1110111 -zunpkd820 31..25=0b1010110 24..20=0b01101 rs1 14..12=0b000 rd 6..0=0b1110111 -zunpkd830 31..25=0b1010110 24..20=0b01110 rs1 14..12=0b000 rd 6..0=0b1110111 -zunpkd831 31..25=0b1010110 24..20=0b01111 rs1 14..12=0b000 rd 6..0=0b1110111 -zunpkd832 31..25=0b1010110 24..20=0b10111 rs1 14..12=0b000 rd 6..0=0b1110111 -add32 31..25=0b0100000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -cras32 31..25=0b0100010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -crsa32 31..25=0b0100011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kabs32 31..25=0b1010110 24..20=0b10010 rs1 14..12=0b000 rd 6..0=0b1110111 -kadd32 31..25=0b0001000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kcras32 31..25=0b0001010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kcrsa32 31..25=0b0001011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kdmbb16 31..25=0b1101101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmbt16 31..25=0b1110101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmtt16 31..25=0b1111101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmabb16 31..25=0b1101100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmabt16 31..25=0b1110100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmatt16 31..25=0b1111100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -khmbb16 31..25=0b1101110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -khmbt16 31..25=0b1110110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -khmtt16 31..25=0b1111110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmabb32 31..25=0b0101101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmabt32 31..25=0b0110101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmatt32 31..25=0b0111101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmaxda32 31..25=0b0100101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmda32 31..25=0b0011100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmxda32 31..25=0b0011101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmads32 31..25=0b0101110 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmadrs32 31..25=0b0110110 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmaxds32 31..25=0b0111110 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmsda32 31..25=0b0100110 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmsxda32 31..25=0b0100111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ksll32 31..25=0b0110010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kslli32 31..25=0b1000010 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 -kslra32 31..25=0b0101011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kslra32.u 31..25=0b0110011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kstas32 31..25=0b1100000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kstsa32 31..25=0b1100001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ksub32 31..25=0b0001001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -pkbb32 31..25=0b0000111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -pkbt32 31..25=0b0001111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -pktt32 31..25=0b0010111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -pktb32 31..25=0b0011111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -radd32 31..25=0b0000000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -rcras32 31..25=0b0000010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -rcrsa32 31..25=0b0000011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -rstas32 31..25=0b1011000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -rstsa32 31..25=0b1011001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -rsub32 31..25=0b0000001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -sll32 31..25=0b0101010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -slli32 31..25=0b0111010 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 -smax32 31..25=0b1001001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -smbt32 31..25=0b0001100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -smtt32 31..25=0b0010100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -smds32 31..25=0b0101100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -smdrs32 31..25=0b0110100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -smxds32 31..25=0b0111100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -smin32 31..25=0b1001000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -sra32 31..25=0b0101000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -sra32.u 31..25=0b0110000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -srai32 31..25=0b0111000 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 -srai32.u 31..25=0b1000000 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 -sraiw.u 31..25=0b0011010 imm5 rs1 14..12=0b001 rd 6..0=0b1110111 -srl32 31..25=0b0101001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -srl32.u 31..25=0b0110001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -srli32 31..25=0b0111001 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 -srli32.u 31..25=0b1000001 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 -stas32 31..25=0b1111000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -stsa32 31..25=0b1111001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -sub32 31..25=0b0100001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ukadd32 31..25=0b0011000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ukcras32 31..25=0b0011010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ukcrsa32 31..25=0b0011011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ukstas32 31..25=0b1110000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ukstsa32 31..25=0b1110001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -uksub32 31..25=0b0011001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -umax32 31..25=0b1010001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -umin32 31..25=0b1010000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -uradd32 31..25=0b0010000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -urcras32 31..25=0b0010010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -urcrsa32 31..25=0b0010011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -urstas32 31..25=0b1101000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -urstsa32 31..25=0b1101001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ursub32 31..25=0b0010001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 diff --git a/unratified/rv32_p b/unratified/rv32_p new file mode 100644 index 0000000..b2172f5 --- /dev/null +++ b/unratified/rv32_p @@ -0,0 +1,3 @@ +add64 31..25=0b1100000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +sub64 31..25=0b1100001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 + diff --git a/unratified/rv64_p b/unratified/rv64_p new file mode 100644 index 0000000..db8ec29 --- /dev/null +++ b/unratified/rv64_p @@ -0,0 +1,81 @@ +add32 31..25=0b0100000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +radd32 31..25=0b0000000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +uradd32 31..25=0b0010000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kadd32 31..25=0b0001000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +ukadd32 31..25=0b0011000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +sub32 31..25=0b0100001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +rsub32 31..25=0b0000001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +ursub32 31..25=0b0010001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +ksub32 31..25=0b0001001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +uksub32 31..25=0b0011001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +cras32 31..25=0b0100010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +rcras32 31..25=0b0000010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +urcras32 31..25=0b0010010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kcras32 31..25=0b0001010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +ukcras32 31..25=0b0011010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +crsa32 31..25=0b0100011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +rcrsa32 31..25=0b0000011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +urcrsa32 31..25=0b0010011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kcrsa32 31..25=0b0001011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +ukcrsa32 31..25=0b0011011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +stas32 31..25=0b1111000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +rstas32 31..25=0b1011000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +urstas32 31..25=0b1101000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kstas32 31..25=0b1100000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +ukstas32 31..25=0b1110000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +stsa32 31..25=0b1111001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +rstsa32 31..25=0b1011001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +urstsa32 31..25=0b1101001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kstsa32 31..25=0b1100001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +ukstsa32 31..25=0b1110001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +sra32 31..25=0b0101000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +srai32 31..25=0b0111000 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 +sra32.u 31..25=0b0110000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +srai32.u 31..25=0b1000000 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 +srl32 31..25=0b0101001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +srli32 31..25=0b0111001 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 +srl32.u 31..25=0b0110001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +srli32.u 31..25=0b1000001 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 +sll32 31..25=0b0101010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +slli32 31..25=0b0111010 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 +ksll32 31..25=0b0110010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kslli32 31..25=0b1000010 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 +kslra32 31..25=0b0101011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kslra32.u 31..25=0b0110011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +smin32 31..25=0b1001000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +umin32 31..25=0b1010000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +smax32 31..25=0b1001001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +umax32 31..25=0b1010001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kabs32 31..25=0b1010110 24..20=0b10010 rs1 14..12=0b000 rd 6..0=0b1110111 +khmbb16 31..25=0b1101110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +khmbt16 31..25=0b1110110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +khmtt16 31..25=0b1111110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmbb16 31..25=0b1101101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmbt16 31..25=0b1110101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmtt16 31..25=0b1111101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmabb16 31..25=0b1101100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmabt16 31..25=0b1110100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmatt16 31..25=0b1111100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +# smbb32 is missing +smbt32 31..25=0b0001100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +smtt32 31..25=0b0010100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kmabb32 31..25=0b0101101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kmabt32 31..25=0b0110101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kmatt32 31..25=0b0111101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kmda32 31..25=0b0011100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kmxda32 31..25=0b0011101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +# kmada32 is missing +kmaxda32 31..25=0b0100101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kmads32 31..25=0b0101110 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kmadrs32 31..25=0b0110110 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kmaxds32 31..25=0b0111110 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kmsda32 31..25=0b0100110 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kmsxda32 31..25=0b0100111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +smds32 31..25=0b0101100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +smdrs32 31..25=0b0110100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +smxds32 31..25=0b0111100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +sraiw.u 31..25=0b0011010 imm5 rs1 14..12=0b001 rd 6..0=0b1110111 +pkbb32 31..25=0b0000111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +pkbt32 31..25=0b0001111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +pktt32 31..25=0b0010111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +pktb32 31..25=0b0011111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 diff --git a/unratified/rv_p b/unratified/rv_p new file mode 100644 index 0000000..c239c10 --- /dev/null +++ b/unratified/rv_p @@ -0,0 +1,245 @@ +add8 31..25=0b0100100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +add16 31..25=0b0100000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ave 31..25=0b1110000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +bitrev 31..25=0b1110011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +bitrevi 31..26=0b111010 imm6 rs1 14..12=0b000 rd 6..0=0b1110111 +bpick rs3 26..25=0b00 rs2 rs1 14..12=0b011 rd 6..0=0b1110111 +clrs8 31..25=0b1010111 24..20=0b00000 rs1 14..12=0b000 rd 6..0=0b1110111 +clrs16 31..25=0b1010111 24..20=0b01000 rs1 14..12=0b000 rd 6..0=0b1110111 +clrs32 31..25=0b1010111 24..20=0b11000 rs1 14..12=0b000 rd 6..0=0b1110111 +clo8 31..25=0b1010111 24..20=0b00011 rs1 14..12=0b000 rd 6..0=0b1110111 +clo16 31..25=0b1010111 24..20=0b01011 rs1 14..12=0b000 rd 6..0=0b1110111 +clo32 31..25=0b1010111 24..20=0b11011 rs1 14..12=0b000 rd 6..0=0b1110111 +clz8 31..25=0b1010111 24..20=0b00001 rs1 14..12=0b000 rd 6..0=0b1110111 +clz16 31..25=0b1010111 24..20=0b01001 rs1 14..12=0b000 rd 6..0=0b1110111 +clz32 31..25=0b1010111 24..20=0b11001 rs1 14..12=0b000 rd 6..0=0b1110111 +cmpeq8 31..25=0b0100111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +cmpeq16 31..25=0b0100110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +cras16 31..25=0b0100010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +crsa16 31..25=0b0100011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +insb 31..25=0b1010110 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 +kabs8 31..25=0b1010110 24..20=0b10000 rs1 14..12=0b000 rd 6..0=0b1110111 +kabs16 31..25=0b1010110 24..20=0b10001 rs1 14..12=0b000 rd 6..0=0b1110111 +kabsw 31..25=0b1010110 24..20=0b10100 rs1 14..12=0b000 rd 6..0=0b1110111 +kadd8 31..25=0b0001100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +kadd16 31..25=0b0001000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +kadd64 31..25=0b1001000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kaddh 31..25=0b0000010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kaddw 31..25=0b0000000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kcras16 31..25=0b0001010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +kcrsa16 31..25=0b0001011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +kdmbb 31..25=0b0000101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmbt 31..25=0b0001101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmtt 31..25=0b0010101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmabb 31..25=0b1101001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmabt 31..25=0b1110001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmatt 31..25=0b1111001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +khm8 31..25=0b1000111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +khmx8 31..25=0b1001111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +khm16 31..25=0b1000011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +khmx16 31..25=0b1001011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +khmbb 31..25=0b0000110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +khmbt 31..25=0b0001110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +khmtt 31..25=0b0010110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmabb 31..25=0b0101101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmabt 31..25=0b0110101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmatt 31..25=0b0111101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmada 31..25=0b0100100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmaxda 31..25=0b0100101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmads 31..25=0b0101110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmadrs 31..25=0b0110110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmaxds 31..25=0b0111110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmar64 31..25=0b1001010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmda 31..25=0b0011100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmxda 31..25=0b0011101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmac 31..25=0b0110000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmac.u 31..25=0b0111000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmawb 31..25=0b0100011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmawb.u 31..25=0b0101011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmawb2 31..25=0b1100111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmawb2.u 31..25=0b1101111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmawt 31..25=0b0110011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmawt.u 31..25=0b0111011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmawt2 31..25=0b1110111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmawt2.u 31..25=0b1111111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmsb 31..25=0b0100001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmsb.u 31..25=0b0101001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmwb2 31..25=0b1000111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmwb2.u 31..25=0b1001111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmwt2 31..25=0b1010111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmwt2.u 31..25=0b1011111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmsda 31..25=0b0100110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmsxda 31..25=0b0100111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmsr64 31..25=0b1001011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +ksllw 31..25=0b0010011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kslliw 31..25=0b0011011 imm5 rs1 14..12=0b001 rd 6..0=0b1110111 +ksll8 31..25=0b0110110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +kslli8 31..25=0b0111110 24..23=0b01 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 +ksll16 31..25=0b0110010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +kslli16 31..25=0b0111010 24=0b1 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 +kslra8 31..25=0b0101111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +kslra8.u 31..25=0b0110111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +kslra16 31..25=0b0101011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +kslra16.u 31..25=0b0110011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +kslraw 31..25=0b0110111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kslraw.u 31..25=0b0111111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kstas16 31..25=0b1100010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kstsa16 31..25=0b1100011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +ksub8 31..25=0b0001101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ksub16 31..25=0b0001001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ksub64 31..25=0b1001001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +ksubh 31..25=0b0000011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +ksubw 31..25=0b0000001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kwmmul 31..25=0b0110001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kwmmul.u 31..25=0b0111001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +maddr32 31..25=0b1100010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +maxw 31..25=0b1111001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +minw 31..25=0b1111000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +msubr32 31..25=0b1100011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +mulr64 31..25=0b1111000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +mulsr64 31..25=0b1110000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +pbsad 31..25=0b1111110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +pbsada 31..25=0b1111111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +pkbb16 31..25=0b0000111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +pkbt16 31..25=0b0001111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +pktt16 31..25=0b0010111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +pktb16 31..25=0b0011111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +radd8 31..25=0b0000100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +radd16 31..25=0b0000000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +radd64 31..25=0b1000000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +raddw 31..25=0b0010000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +rcras16 31..25=0b0000010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +rcrsa16 31..25=0b0000011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +rstas16 31..25=0b1011010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +rstsa16 31..25=0b1011011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +rsub8 31..25=0b0000101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +rsub16 31..25=0b0000001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +rsub64 31..25=0b1000001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +rsubw 31..25=0b0010001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +sclip8 31..25=0b1000110 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 +sclip16 31..25=0b1000010 24=0b0 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 +sclip32 31..25=0b1110010 imm5 rs1 14..12=0b000 rd 6..0=0b1110111 +scmple8 31..25=0b0001111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +scmple16 31..25=0b0001110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +scmplt8 31..25=0b0000111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +scmplt16 31..25=0b0000110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +sll8 31..25=0b0101110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +slli8 31..25=0b0111110 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 +sll16 31..25=0b0101010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +slli16 31..25=0b0111010 24=0b0 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 +smal 31..25=0b0101111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smalbb 31..25=0b1000100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smalbt 31..25=0b1001100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smaltt 31..25=0b1010100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smalda 31..25=0b1000110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smalxda 31..25=0b1001110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smalds 31..25=0b1000101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smaldrs 31..25=0b1001101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smalxds 31..25=0b1010101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smar64 31..25=0b1000010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smaqa 31..25=0b1100100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +smaqa.su 31..25=0b1100101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +smax8 31..25=0b1000101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +smax16 31..25=0b1000001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +smbb16 31..25=0b0000100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smbt16 31..25=0b0001100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smtt16 31..25=0b0010100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smds 31..25=0b0101100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smdrs 31..25=0b0110100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smxds 31..25=0b0111100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smin8 31..25=0b1000100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +smin16 31..25=0b1000000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +smmul 31..25=0b0100000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smmul.u 31..25=0b0101000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smmwb 31..25=0b0100010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smmwb.u 31..25=0b0101010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smmwt 31..25=0b0110010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smmwt.u 31..25=0b0111010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smslda 31..25=0b1010110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smslxda 31..25=0b1011110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smsr64 31..25=0b1000011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smul8 31..25=0b1010100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +smulx8 31..25=0b1010101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +smul16 31..25=0b1010000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +smulx16 31..25=0b1010001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +sra.u 31..25=0b0010010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +srai.u 31..26=0b110101 imm6 rs1 14..12=0b001 rd 6..0=0b1110111 +sra8 31..25=0b0101100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +sra8.u 31..25=0b0110100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +srai8 31..25=0b0111100 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 +srai8.u 31..25=0b0111100 24..23=0b01 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 +sra16 31..25=0b0101000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +sra16.u 31..25=0b0110000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +srai16 31..25=0b0111000 24=0b0 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 +srai16.u 31..25=0b0111000 24=0b1 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 +srl8 31..25=0b0101101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +srl8.u 31..25=0b0110101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +srli8 31..25=0b0111101 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 +srli8.u 31..25=0b0111101 24..23=0b01 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 +srl16 31..25=0b0101001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +srl16.u 31..25=0b0110001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +srli16 31..25=0b0111001 24=0b0 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 +srli16.u 31..25=0b0111001 24=0b1 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 +stas16 31..25=0b1111010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +stsa16 31..25=0b1111011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +sub8 31..25=0b0100101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +sub16 31..25=0b0100001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +sunpkd810 31..25=0b1010110 24..20=0b01000 rs1 14..12=0b000 rd 6..0=0b1110111 +sunpkd820 31..25=0b1010110 24..20=0b01001 rs1 14..12=0b000 rd 6..0=0b1110111 +sunpkd830 31..25=0b1010110 24..20=0b01010 rs1 14..12=0b000 rd 6..0=0b1110111 +sunpkd831 31..25=0b1010110 24..20=0b01011 rs1 14..12=0b000 rd 6..0=0b1110111 +sunpkd832 31..25=0b1010110 24..20=0b10011 rs1 14..12=0b000 rd 6..0=0b1110111 +swap8 31..25=0b1010110 24..20=0b11000 rs1 14..12=0b000 rd 6..0=0b1110111 +uclip8 31..25=0b1000110 24..23=0b10 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 +uclip16 31..25=0b1000010 24=0b1 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 +uclip32 31..25=0b1111010 imm5 rs1 14..12=0b000 rd 6..0=0b1110111 +ucmple8 31..25=0b0011111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ucmple16 31..25=0b0011110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ucmplt8 31..25=0b0010111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ucmplt16 31..25=0b0010110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ukadd8 31..25=0b0011100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ukadd16 31..25=0b0011000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ukadd64 31..25=0b1011000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +ukaddh 31..25=0b0001010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +ukaddw 31..25=0b0001000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +ukcras16 31..25=0b0011010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ukcrsa16 31..25=0b0011011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ukmar64 31..25=0b1011010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +ukmsr64 31..25=0b1011011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +ukstas16 31..25=0b1110010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +ukstsa16 31..25=0b1110011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +uksub8 31..25=0b0011101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +uksub16 31..25=0b0011001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +uksub64 31..25=0b1011001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +uksubh 31..25=0b0001011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +uksubw 31..25=0b0001001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +umar64 31..25=0b1010010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +umaqa 31..25=0b1100110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +umax8 31..25=0b1001101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +umax16 31..25=0b1001001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +umin8 31..25=0b1001100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +umin16 31..25=0b1001000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +umsr64 31..25=0b1010011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +umul8 31..25=0b1011100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +umulx8 31..25=0b1011101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +umul16 31..25=0b1011000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +umulx16 31..25=0b1011001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +uradd8 31..25=0b0010100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +uradd16 31..25=0b0010000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +uradd64 31..25=0b1010000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +uraddw 31..25=0b0011000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +urcras16 31..25=0b0010010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +urcrsa16 31..25=0b0010011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +urstas16 31..25=0b1101010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +urstsa16 31..25=0b1101011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +ursub8 31..25=0b0010101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ursub16 31..25=0b0010001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ursub64 31..25=0b1010001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +ursubw 31..25=0b0011001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +wexti 31..25=0b1101111 imm5 rs1 14..12=0b000 rd 6..0=0b1110111 +wext 31..25=0b1100111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +zunpkd810 31..25=0b1010110 24..20=0b01100 rs1 14..12=0b000 rd 6..0=0b1110111 +zunpkd820 31..25=0b1010110 24..20=0b01101 rs1 14..12=0b000 rd 6..0=0b1110111 +zunpkd830 31..25=0b1010110 24..20=0b01110 rs1 14..12=0b000 rd 6..0=0b1110111 +zunpkd831 31..25=0b1010110 24..20=0b01111 rs1 14..12=0b000 rd 6..0=0b1110111 +zunpkd832 31..25=0b1010110 24..20=0b10111 rs1 14..12=0b000 rd 6..0=0b1110111 diff --git a/unratified/rv_zbp b/unratified/rv_zbp new file mode 100644 index 0000000..810fe9d --- /dev/null +++ b/unratified/rv_zbp @@ -0,0 +1,15 @@ +$import rv_zbb::andn +$import rv_zbb::orn +$import rv_zbb::xnor +$import rv_zbe::pack +$import rv_zbe::packh +$import rv_zbb::rol +$import rv_zbb::ror +grev rd rs1 rs2 31..25=52 14..12=5 6..2=0x0C 1..0=3 +gorc rd rs1 rs2 31..25=20 14..12=5 6..2=0x0C 1..0=3 +shfl rd rs1 rs2 31..25=4 14..12=1 6..2=0x0C 1..0=3 +unshfl rd rs1 rs2 31..25=4 14..12=5 6..2=0x0C 1..0=3 +xperm.n rd rs1 rs2 31..25=20 14..12=2 6..2=0x0C 1..0=3 +xperm.b rd rs1 rs2 31..25=20 14..12=4 6..2=0x0C 1..0=3 +xperm.h rd rs1 rs2 31..25=20 14..12=6 6..2=0x0C 1..0=3 +packu rd rs1 rs2 31..25=36 14..12=4 6..2=0x0C 1..0=3 diff --git a/unratified/rv_zbpbo b/unratified/rv_zbpbo new file mode 100644 index 0000000..356fbb2 --- /dev/null +++ b/unratified/rv_zbpbo @@ -0,0 +1,6 @@ +$import rv_zbe::pack +$import rv_zbp::packu +$import rv_zbb::max +$import rv_zbb::min +$import rv_zbt::cmix +$pseudo_op rv64_zbp::grevi rev8.h rd rs1 31..20=0x688 14..12=5 6..0=0x13 -- cgit v1.1 From 7db73f2163ea17a48b7e513d65d7eac6be277854 Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 18:40:07 +0530 Subject: migrate Zbkb-extension opcodes - split instruction based on new file naming policy - import instructions present in other ratified and unratified extensions - pseudo ops from zbp and zbb defined --- opcodes-rv32zbkb | 8 -------- opcodes-rv64zbkb | 3 --- rv32_zbkb | 4 ++++ rv64_zbkb | 6 ++++++ rv_zbkb | 8 ++++++++ 5 files changed, 18 insertions(+), 11 deletions(-) delete mode 100644 opcodes-rv32zbkb delete mode 100644 opcodes-rv64zbkb create mode 100644 rv32_zbkb create mode 100644 rv64_zbkb create mode 100644 rv_zbkb diff --git a/opcodes-rv32zbkb b/opcodes-rv32zbkb deleted file mode 100644 index 5c9e2d5..0000000 --- a/opcodes-rv32zbkb +++ /dev/null @@ -1,8 +0,0 @@ -# This file includes only the RV32Zbkb instructions that are not in RV32Zbb - -pack rd rs1 rs2 31..25=4 14..12=4 6..2=0x0C 1..0=3 -packh rd rs1 rs2 31..25=4 14..12=7 6..2=0x0C 1..0=3 - -brev8 rd rs1 31..26=26 25..20=7 14..12=5 6..2=0x04 1..0=3 -unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=0x04 1..0=3 -zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=0x04 1..0=3 diff --git a/opcodes-rv64zbkb b/opcodes-rv64zbkb deleted file mode 100644 index 1c3146d..0000000 --- a/opcodes-rv64zbkb +++ /dev/null @@ -1,3 +0,0 @@ -# This file includes only the RV64Zbkb instructions that are not in RV64Zbb - -packw rd rs1 rs2 31..25=4 14..12=4 6..2=0x0E 1..0=3 diff --git a/rv32_zbkb b/rv32_zbkb new file mode 100644 index 0000000..f791453 --- /dev/null +++ b/rv32_zbkb @@ -0,0 +1,4 @@ +$pseudo_op rv64_zbp::shfli zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=4 1..0=3 +$pseudo_op rv64_zbp::unshfli unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=4 1..0=3 +$pseudo_op rv64_zbb::rori rori rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x698 14..12=5 6..0=0x13 diff --git a/rv64_zbkb b/rv64_zbkb new file mode 100644 index 0000000..ad2f4a9 --- /dev/null +++ b/rv64_zbkb @@ -0,0 +1,6 @@ +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 +$import rv64_zbb::rolw +$import rv64_zbb::rorw +$import rv64_zbb::roriw +$import rv64_zbb::rori +$import rv64_zbe::packw diff --git a/rv_zbkb b/rv_zbkb new file mode 100644 index 0000000..1499d78 --- /dev/null +++ b/rv_zbkb @@ -0,0 +1,8 @@ +$import rv_zbb::rol +$import rv_zbb::ror +$import rv_zbb::andn +$import rv_zbb::orn +$import rv_zbb::xnor +$import rv_zbe::pack +$import rv_zbe::packh +$pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 -- cgit v1.1 From 25f4c905a52dcb32e25a32b2bfe207dc861fbab5 Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 19:05:22 +0530 Subject: migrate Zbkx-Extension opcodes --- opcodes-rv32zbkx | 2 -- rv_zbkx | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) delete mode 100644 opcodes-rv32zbkx create mode 100644 rv_zbkx diff --git a/opcodes-rv32zbkx b/opcodes-rv32zbkx deleted file mode 100644 index 12bc0b4..0000000 --- a/opcodes-rv32zbkx +++ /dev/null @@ -1,2 +0,0 @@ -xperm4 rd rs1 rs2 31..25=20 14..12=2 6..2=0x0C 1..0=3 -xperm8 rd rs1 rs2 31..25=20 14..12=4 6..2=0x0C 1..0=3 diff --git a/rv_zbkx b/rv_zbkx new file mode 100644 index 0000000..12bc0b4 --- /dev/null +++ b/rv_zbkx @@ -0,0 +1,2 @@ +xperm4 rd rs1 rs2 31..25=20 14..12=2 6..2=0x0C 1..0=3 +xperm8 rd rs1 rs2 31..25=20 14..12=4 6..2=0x0C 1..0=3 -- cgit v1.1 From 9a255844c2726ed301fd4fc9371489f4901d30b0 Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 19:10:52 +0530 Subject: migrate unratified bitmanip opcodes - split instructions as per new file naming policy - move all instructions to unratified directory - includes rv[64|32]_zbp[bo] (missed in previous commit while migrating P-extension) --- opcodes-rv32xbitmanip | 42 ------------------------------------------ opcodes-rv64xbitmanip | 35 ----------------------------------- unratified/rv32_zbp | 7 +++++++ unratified/rv32_zbpbo | 5 +++++ unratified/rv32_zbt | 2 ++ unratified/rv64_zbe | 4 ++++ unratified/rv64_zbf | 3 +++ unratified/rv64_zbm | 7 +++++++ unratified/rv64_zbp | 17 +++++++++++++++++ unratified/rv64_zbpbo | 2 ++ unratified/rv64_zbr | 3 +++ unratified/rv64_zbt | 6 ++++++ unratified/rv_zbe | 5 +++++ unratified/rv_zbf | 4 ++++ unratified/rv_zbr | 7 +++++++ unratified/rv_zbt | 6 ++++++ 16 files changed, 78 insertions(+), 77 deletions(-) delete mode 100644 opcodes-rv32xbitmanip delete mode 100644 opcodes-rv64xbitmanip create mode 100644 unratified/rv32_zbp create mode 100644 unratified/rv32_zbpbo create mode 100644 unratified/rv32_zbt create mode 100644 unratified/rv64_zbe create mode 100644 unratified/rv64_zbf create mode 100644 unratified/rv64_zbm create mode 100644 unratified/rv64_zbp create mode 100644 unratified/rv64_zbpbo create mode 100644 unratified/rv64_zbr create mode 100644 unratified/rv64_zbt create mode 100644 unratified/rv_zbe create mode 100644 unratified/rv_zbf create mode 100644 unratified/rv_zbr create mode 100644 unratified/rv_zbt diff --git a/opcodes-rv32xbitmanip b/opcodes-rv32xbitmanip deleted file mode 100644 index 173fb8c..0000000 --- a/opcodes-rv32xbitmanip +++ /dev/null @@ -1,42 +0,0 @@ -# This file contains unratified instructions that have been proposed -# by the Bit Manipulation TG but have not been ratified. (Spike -# supports them via the Xbitmanip extension, hence the filename.) - -slo rd rs1 rs2 31..25=16 14..12=1 6..2=0x0C 1..0=3 -sro rd rs1 rs2 31..25=16 14..12=5 6..2=0x0C 1..0=3 - -gorc rd rs1 rs2 31..25=20 14..12=5 6..2=0x0C 1..0=3 -grev rd rs1 rs2 31..25=52 14..12=5 6..2=0x0C 1..0=3 - -sloi rd rs1 31..26=8 shamt 14..12=1 6..2=0x04 1..0=3 -sroi rd rs1 31..26=8 shamt 14..12=5 6..2=0x04 1..0=3 - -# These are marked as pseudos to avoid conflicting with orc.b and rev8 -@gorci rd rs1 31..26=10 shamt 14..12=5 6..2=0x04 1..0=3 -@grevi rd rs1 31..26=26 shamt 14..12=5 6..2=0x04 1..0=3 - -cmix rd rs1 rs2 rs3 26..25=3 14..12=1 6..2=0x0C 1..0=3 -cmov rd rs1 rs2 rs3 26..25=3 14..12=5 6..2=0x0C 1..0=3 - -fsl rd rs1 rs2 rs3 26..25=2 14..12=1 6..2=0x0C 1..0=3 -fsr rd rs1 rs2 rs3 26..25=2 14..12=5 6..2=0x0C 1..0=3 -fsri rd rs1 shamt rs3 26=1 14..12=5 6..2=0x04 1..0=3 - -crc32.b rd rs1 31..20=0x610 14..12=1 6..2=0x04 1..0=3 -crc32.h rd rs1 31..20=0x611 14..12=1 6..2=0x04 1..0=3 -crc32.w rd rs1 31..20=0x612 14..12=1 6..2=0x04 1..0=3 -crc32c.b rd rs1 31..20=0x618 14..12=1 6..2=0x04 1..0=3 -crc32c.h rd rs1 31..20=0x619 14..12=1 6..2=0x04 1..0=3 -crc32c.w rd rs1 31..20=0x61A 14..12=1 6..2=0x04 1..0=3 - -shfl rd rs1 rs2 31..25=4 14..12=1 6..2=0x0C 1..0=3 -unshfl rd rs1 rs2 31..25=4 14..12=5 6..2=0x0C 1..0=3 -bcompress rd rs1 rs2 31..25=4 14..12=6 6..2=0x0C 1..0=3 -bdecompress rd rs1 rs2 31..25=36 14..12=6 6..2=0x0C 1..0=3 -packu rd rs1 rs2 31..25=36 14..12=4 6..2=0x0C 1..0=3 -bfp rd rs1 rs2 31..25=36 14..12=7 6..2=0x0C 1..0=3 - -shfli rd rs1 31..25=4 shamtw 14..12=1 6..2=0x04 1..0=3 -unshfli rd rs1 31..25=4 shamtw 14..12=5 6..2=0x04 1..0=3 - -xperm16 rd rs1 rs2 31..25=20 14..12=6 6..2=0x0C 1..0=3 diff --git a/opcodes-rv64xbitmanip b/opcodes-rv64xbitmanip deleted file mode 100644 index 6e6a595..0000000 --- a/opcodes-rv64xbitmanip +++ /dev/null @@ -1,35 +0,0 @@ -# This file contains unratified instructions that have been proposed -# by the Bit Manipulation TG but have not been ratified. (Spike -# supports them via the Xbitmanip extension, hence the filename.) - -bmatflip rd rs1 31..20=0x603 14..12=1 6..2=0x04 1..0=3 -crc32.d rd rs1 31..20=0x613 14..12=1 6..2=0x04 1..0=3 -crc32c.d rd rs1 31..20=0x61B 14..12=1 6..2=0x04 1..0=3 - -bmator rd rs1 rs2 31..25=4 14..12=3 6..2=0x0C 1..0=3 -bmatxor rd rs1 rs2 31..25=36 14..12=3 6..2=0x0C 1..0=3 - -slow rd rs1 rs2 31..25=16 14..12=1 6..2=0x0E 1..0=3 -srow rd rs1 rs2 31..25=16 14..12=5 6..2=0x0E 1..0=3 - -gorcw rd rs1 rs2 31..25=20 14..12=5 6..2=0x0E 1..0=3 -grevw rd rs1 rs2 31..25=52 14..12=5 6..2=0x0E 1..0=3 - -sloiw rd rs1 31..26=8 25=0 shamtw 14..12=1 6..2=0x06 1..0=3 -sroiw rd rs1 31..26=8 25=0 shamtw 14..12=5 6..2=0x06 1..0=3 - -gorciw rd rs1 31..26=10 25=0 shamtw 14..12=5 6..2=0x06 1..0=3 -greviw rd rs1 31..26=26 25=0 shamtw 14..12=5 6..2=0x06 1..0=3 - -fslw rd rs1 rs2 rs3 26..25=2 14..12=1 6..2=0x0E 1..0=3 -fsrw rd rs1 rs2 rs3 26..25=2 14..12=5 6..2=0x0E 1..0=3 -fsriw rd rs1 shamtw rs3 26..25=2 14..12=5 6..2=0x06 1..0=3 - -shflw rd rs1 rs2 31..25=4 14..12=1 6..2=0x0E 1..0=3 -unshflw rd rs1 rs2 31..25=4 14..12=5 6..2=0x0E 1..0=3 -bcompressw rd rs1 rs2 31..25=4 14..12=6 6..2=0x0E 1..0=3 -bdecompressw rd rs1 rs2 31..25=36 14..12=6 6..2=0x0E 1..0=3 -packuw rd rs1 rs2 31..25=36 14..12=4 6..2=0x0E 1..0=3 -bfpw rd rs1 rs2 31..25=36 14..12=7 6..2=0x0E 1..0=3 - -xperm32 rd rs1 rs2 31..25=20 14..12=0 6..2=0x0C 1..0=3 diff --git a/unratified/rv32_zbp b/unratified/rv32_zbp new file mode 100644 index 0000000..ac8a564 --- /dev/null +++ b/unratified/rv32_zbp @@ -0,0 +1,7 @@ +$pseudo_op rv64_zbp::grevi grevi rd rs1 31..25=0x34 shamtw 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbp::gorci gorci rd rs1 31..25=0x14 shamtw 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbp::shfli shfli rd rs1 31..25=4 24=0 shamtw4 14..12=1 6..2=0x04 1..0=3 +$pseudo_op rv64_zbp::unshfli unshfli rd rs1 31..25=4 24=0 shamtw4 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbb::rori rori rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 + + diff --git a/unratified/rv32_zbpbo b/unratified/rv32_zbpbo new file mode 100644 index 0000000..6ecc566 --- /dev/null +++ b/unratified/rv32_zbpbo @@ -0,0 +1,5 @@ +$import rv_zbb::clz +$import rv_zbt::fsr +$import rv32_zbt::fsri +$pseudo_op rv64_zbp::grevi rev rd rs1 31..20=0x69F 14..12=5 6..0=0x13 + diff --git a/unratified/rv32_zbt b/unratified/rv32_zbt new file mode 100644 index 0000000..4b5a286 --- /dev/null +++ b/unratified/rv32_zbt @@ -0,0 +1,2 @@ +$pseudo_op rv64_zbt::fsri fsri rd rs1 rs3 26=1 25=0 shamtw 14..12=5 6..2=0x04 1..0=3 + diff --git a/unratified/rv64_zbe b/unratified/rv64_zbe new file mode 100644 index 0000000..d36b80c --- /dev/null +++ b/unratified/rv64_zbe @@ -0,0 +1,4 @@ +bcompressw rd rs1 rs2 31..25=4 14..12=6 6..2=0x0E 1..0=3 +bdecompressw rd rs1 rs2 31..25=36 14..12=6 6..2=0x0E 1..0=3 +packw rd rs1 rs2 31..25=4 14..12=4 6..2=0x0E 1..0=3 + diff --git a/unratified/rv64_zbf b/unratified/rv64_zbf new file mode 100644 index 0000000..d02b59d --- /dev/null +++ b/unratified/rv64_zbf @@ -0,0 +1,3 @@ +bfpw rd rs1 rs2 31..25=36 14..12=7 6..2=0x0E 1..0=3 +$import rv64_zbe::packw + diff --git a/unratified/rv64_zbm b/unratified/rv64_zbm new file mode 100644 index 0000000..46a5ebf --- /dev/null +++ b/unratified/rv64_zbm @@ -0,0 +1,7 @@ +bmatflip rd rs1 31..20=0x603 14..12=1 6..2=0x04 1..0=3 +bmator rd rs1 rs2 31..25=4 14..12=3 6..2=0x0C 1..0=3 +bmatxor rd rs1 rs2 31..25=36 14..12=3 6..2=0x0C 1..0=3 +$pseudo_op rv64_zbp::unshfli unzip16 rd rs1 31..25=4 24..20=16 14..12=5 6..2=4 1..0=3 +$pseudo_op rv64_zbp::unshfli unzip8 rd rs1 31..25=4 24..20=24 14..12=5 6..2=4 1..0=3 +$import rv_zbe::pack +$import rv_zbp::packu diff --git a/unratified/rv64_zbp b/unratified/rv64_zbp new file mode 100644 index 0000000..f4c0bca --- /dev/null +++ b/unratified/rv64_zbp @@ -0,0 +1,17 @@ +grevi rd rs1 31..26=26 shamt 14..12=5 6..2=0x04 1..0=3 +gorci rd rs1 31..26=10 shamt 14..12=5 6..2=0x04 1..0=3 +shfli rd rs1 31..26=2 25=0 shamtw 14..12=1 6..2=0x04 1..0=3 +unshfli rd rs1 31..26=2 25=0 shamtw 14..12=5 6..2=0x04 1..0=3 +$import rv64_zbe::packw +packuw rd rs1 rs2 31..25=36 14..12=4 6..2=0x0E 1..0=3 +$import rv64_zbb::rolw +$import rv64_zbb::rorw +$import rv64_zbb::roriw +$import rv64_zbb::rori +gorcw rd rs1 rs2 31..25=20 14..12=5 6..2=0x0E 1..0=3 +grevw rd rs1 rs2 31..25=52 14..12=5 6..2=0x0E 1..0=3 +gorciw rd rs1 31..26=10 25=0 shamtw 14..12=5 6..2=0x06 1..0=3 +greviw rd rs1 31..26=26 25=0 shamtw 14..12=5 6..2=0x06 1..0=3 +shflw rd rs1 rs2 31..25=4 14..12=1 6..2=0x0E 1..0=3 +unshflw rd rs1 rs2 31..25=4 14..12=5 6..2=0x0E 1..0=3 +xperm.w rd rs1 rs2 31..25=20 14..12=0 6..2=0x0C 1..0=3 diff --git a/unratified/rv64_zbpbo b/unratified/rv64_zbpbo new file mode 100644 index 0000000..f88bd03 --- /dev/null +++ b/unratified/rv64_zbpbo @@ -0,0 +1,2 @@ +$import rv64_zbt::fsrw +$pseudo_op rv64_zbp::grevi rev rd rs1 31..20=0x6BF 14..12=5 6..0=0x13 diff --git a/unratified/rv64_zbr b/unratified/rv64_zbr new file mode 100644 index 0000000..3b470f1 --- /dev/null +++ b/unratified/rv64_zbr @@ -0,0 +1,3 @@ +crc32.d rd rs1 31..20=0x613 14..12=1 6..2=0x04 1..0=3 +crc32c.d rd rs1 31..20=0x61B 14..12=1 6..2=0x04 1..0=3 + diff --git a/unratified/rv64_zbt b/unratified/rv64_zbt new file mode 100644 index 0000000..fcb84b5 --- /dev/null +++ b/unratified/rv64_zbt @@ -0,0 +1,6 @@ +fslw rd rs1 rs2 rs3 26..25=2 14..12=1 6..2=0x0E 1..0=3 +fsrw rd rs1 rs2 rs3 26..25=2 14..12=5 6..2=0x0E 1..0=3 +fsriw rd rs1 rs3 26..25=2 shamtw 14..12=5 6..2=0x06 1..0=3 +fsri rd rs1 rs3 26=1 shamt 14..12=5 6..2=0x04 1..0=3 + + diff --git a/unratified/rv_zbe b/unratified/rv_zbe new file mode 100644 index 0000000..1e8a037 --- /dev/null +++ b/unratified/rv_zbe @@ -0,0 +1,5 @@ +bcompress rd rs1 rs2 31..25=4 14..12=6 6..2=0x0C 1..0=3 +bdecompress rd rs1 rs2 31..25=36 14..12=6 6..2=0x0C 1..0=3 +pack rd rs1 rs2 31..25=4 14..12=4 6..2=0x0C 1..0=3 +packh rd rs1 rs2 31..25=4 14..12=7 6..2=0x0C 1..0=3 + diff --git a/unratified/rv_zbf b/unratified/rv_zbf new file mode 100644 index 0000000..33dd0a6 --- /dev/null +++ b/unratified/rv_zbf @@ -0,0 +1,4 @@ +bfp rd rs1 rs2 31..25=36 14..12=7 6..2=0x0C 1..0=3 +$import rv_zbe::pack +$import rv_zbe::packh + diff --git a/unratified/rv_zbr b/unratified/rv_zbr new file mode 100644 index 0000000..3cfd5a7 --- /dev/null +++ b/unratified/rv_zbr @@ -0,0 +1,7 @@ +crc32.b rd rs1 31..20=0x610 14..12=1 6..2=0x04 1..0=3 +crc32.h rd rs1 31..20=0x611 14..12=1 6..2=0x04 1..0=3 +crc32.w rd rs1 31..20=0x612 14..12=1 6..2=0x04 1..0=3 +crc32c.b rd rs1 31..20=0x618 14..12=1 6..2=0x04 1..0=3 +crc32c.h rd rs1 31..20=0x619 14..12=1 6..2=0x04 1..0=3 +crc32c.w rd rs1 31..20=0x61A 14..12=1 6..2=0x04 1..0=3 + diff --git a/unratified/rv_zbt b/unratified/rv_zbt new file mode 100644 index 0000000..9e7b98b --- /dev/null +++ b/unratified/rv_zbt @@ -0,0 +1,6 @@ +cmix rd rs1 rs2 rs3 26..25=3 14..12=1 6..2=0x0C 1..0=3 +cmov rd rs1 rs2 rs3 26..25=3 14..12=5 6..2=0x0C 1..0=3 + +fsl rd rs1 rs2 rs3 26..25=2 14..12=1 6..2=0x0C 1..0=3 +fsr rd rs1 rs2 rs3 26..25=2 14..12=5 6..2=0x0C 1..0=3 + -- cgit v1.1 From 98ef45900fbdbe1edf0ce9220e08d60b2912233e Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 19:14:00 +0530 Subject: migrate Zk*-extension opcodes (major) - significant restructuring of opcodes into files as per new file naming policy --- opcodes-rv32zk | 20 -------------------- opcodes-rv64zk | 21 --------------------- opcodes-rvzk | 20 -------------------- rv32_zk | 25 +++++++++++++++++++++++++ rv32_zkn | 25 +++++++++++++++++++++++++ rv32_zknd | 4 ++++ rv32_zkne | 5 +++++ rv32_zknh | 8 ++++++++ rv32_zks | 6 ++++++ rv64_zk | 28 ++++++++++++++++++++++++++++ rv64_zkn | 28 ++++++++++++++++++++++++++++ rv64_zknd | 7 +++++++ rv64_zkne | 5 +++++ rv64_zknh | 6 ++++++ rv64_zks | 7 +++++++ rv_zk | 24 ++++++++++++++++++++++++ rv_zkn | 24 ++++++++++++++++++++++++ rv_zknh | 5 +++++ rv_zks | 26 ++++++++++++++++++++++++++ rv_zksed | 4 ++++ rv_zksh | 4 ++++ 21 files changed, 241 insertions(+), 61 deletions(-) delete mode 100644 opcodes-rv32zk delete mode 100644 opcodes-rv64zk delete mode 100644 opcodes-rvzk create mode 100644 rv32_zk create mode 100644 rv32_zkn create mode 100644 rv32_zknd create mode 100644 rv32_zkne create mode 100644 rv32_zknh create mode 100644 rv32_zks create mode 100644 rv64_zk create mode 100644 rv64_zkn create mode 100644 rv64_zknd create mode 100644 rv64_zkne create mode 100644 rv64_zknh create mode 100644 rv64_zks create mode 100644 rv_zk create mode 100644 rv_zkn create mode 100644 rv_zknh create mode 100644 rv_zks create mode 100644 rv_zksed create mode 100644 rv_zksh diff --git a/opcodes-rv32zk b/opcodes-rv32zk deleted file mode 100644 index 56ed607..0000000 --- a/opcodes-rv32zk +++ /dev/null @@ -1,20 +0,0 @@ - -# -# This file contains opcode specifications for the RISC-V -# Scalar Cryptographic instruction set extension. -# These instructions appear _only_ in RV32. -# ------------------------------------------------------------ - -# Scalar AES - RV32 -aes32esmi rd rs1 rs2 bs 29..25=0b10011 14..12=0 6..0=0x33 -aes32esi rd rs1 rs2 bs 29..25=0b10001 14..12=0 6..0=0x33 -aes32dsmi rd rs1 rs2 bs 29..25=0b10111 14..12=0 6..0=0x33 -aes32dsi rd rs1 rs2 bs 29..25=0b10101 14..12=0 6..0=0x33 - -# Scalar SHA512 - RV32 -sha512sum0r rd rs1 rs2 31..30=1 29..25=0b01000 14..12=0 6..0=0x33 -sha512sum1r rd rs1 rs2 31..30=1 29..25=0b01001 14..12=0 6..0=0x33 -sha512sig0l rd rs1 rs2 31..30=1 29..25=0b01010 14..12=0 6..0=0x33 -sha512sig0h rd rs1 rs2 31..30=1 29..25=0b01110 14..12=0 6..0=0x33 -sha512sig1l rd rs1 rs2 31..30=1 29..25=0b01011 14..12=0 6..0=0x33 -sha512sig1h rd rs1 rs2 31..30=1 29..25=0b01111 14..12=0 6..0=0x33 diff --git a/opcodes-rv64zk b/opcodes-rv64zk deleted file mode 100644 index 85fac51..0000000 --- a/opcodes-rv64zk +++ /dev/null @@ -1,21 +0,0 @@ - -# -# This file contains opcode specifications for the RISC-V -# Scalar Cryptographic instruction set extension. -# These instructions appear _only_ in RV64. -# ------------------------------------------------------------ - -# Scalar AES - RV64 -aes64ks1i rd rs1 rnum 31..30=0 29..25=0b11000 24=1 14..12=0b001 6..0=0x13 -aes64im rd rs1 31..30=0 29..25=0b11000 24..20=0b0000 14..12=0b001 6..0=0x13 -aes64ks2 rd rs1 rs2 31..30=1 29..25=0b11111 14..12=0b000 6..0=0x33 -aes64esm rd rs1 rs2 31..30=0 29..25=0b11011 14..12=0b000 6..0=0x33 -aes64es rd rs1 rs2 31..30=0 29..25=0b11001 14..12=0b000 6..0=0x33 -aes64dsm rd rs1 rs2 31..30=0 29..25=0b11111 14..12=0b000 6..0=0x33 -aes64ds rd rs1 rs2 31..30=0 29..25=0b11101 14..12=0b000 6..0=0x33 - -# Scalar SHA512 - RV64 -sha512sum0 rd rs1 31..30=0 29..25=0b01000 24..20=0b00100 14..12=1 6..0=0x13 -sha512sum1 rd rs1 31..30=0 29..25=0b01000 24..20=0b00101 14..12=1 6..0=0x13 -sha512sig0 rd rs1 31..30=0 29..25=0b01000 24..20=0b00110 14..12=1 6..0=0x13 -sha512sig1 rd rs1 31..30=0 29..25=0b01000 24..20=0b00111 14..12=1 6..0=0x13 diff --git a/opcodes-rvzk b/opcodes-rvzk deleted file mode 100644 index 956a97d..0000000 --- a/opcodes-rvzk +++ /dev/null @@ -1,20 +0,0 @@ - -# -# This file contains opcode specifications for the RISC-V -# Scalar Cryptographic instruction set extension. -# These instructions appear in _both_ RV32 and RV64. -# ------------------------------------------------------------ - -# Scalar SM4 - RV32, RV64 -sm4ed rd rs1 rs2 bs 29..25=0b11000 14..12=0 6..0=0x33 -sm4ks rd rs1 rs2 bs 29..25=0b11010 14..12=0 6..0=0x33 - -# Scalar SM3 - RV32, RV64 -sm3p0 rd rs1 31..30=0 29..25=0b01000 24..20=0b01000 14..12=1 6..0=0x13 -sm3p1 rd rs1 31..30=0 29..25=0b01000 24..20=0b01001 14..12=1 6..0=0x13 - -# Scalar SHA256 - RV32/RV64 -sha256sum0 rd rs1 31..30=0 29..25=0b01000 24..20=0b00000 14..12=1 6..0=0x13 -sha256sum1 rd rs1 31..30=0 29..25=0b01000 24..20=0b00001 14..12=1 6..0=0x13 -sha256sig0 rd rs1 31..30=0 29..25=0b01000 24..20=0b00010 14..12=1 6..0=0x13 -sha256sig1 rd rs1 31..30=0 29..25=0b01000 24..20=0b00011 14..12=1 6..0=0x13 diff --git a/rv32_zk b/rv32_zk new file mode 100644 index 0000000..e491103 --- /dev/null +++ b/rv32_zk @@ -0,0 +1,25 @@ +#import zbkb +$pseudo_op rv64_zbp::shfli zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=4 1..0=3 +$pseudo_op rv64_zbp::unshfli unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=4 1..0=3 +$pseudo_op rv64_zbb::rori rori rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x698 14..12=5 6..0=0x13 + +#import zkne +$import rv32_zkne::aes32esmi +$import rv32_zkne::aes32esi + +#import zknd +# Scalar AES - RV32 +$import rv32_zknd::aes32dsmi +$import rv32_zknd::aes32dsi + + +#import zknh +# Scalar SHA512 - RV32 +$import rv32_zknh::sha512sum0r +$import rv32_zknh::sha512sum1r +$import rv32_zknh::sha512sig0l +$import rv32_zknh::sha512sig0h +$import rv32_zknh::sha512sig1l +$import rv32_zknh::sha512sig1h + diff --git a/rv32_zkn b/rv32_zkn new file mode 100644 index 0000000..e491103 --- /dev/null +++ b/rv32_zkn @@ -0,0 +1,25 @@ +#import zbkb +$pseudo_op rv64_zbp::shfli zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=4 1..0=3 +$pseudo_op rv64_zbp::unshfli unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=4 1..0=3 +$pseudo_op rv64_zbb::rori rori rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x698 14..12=5 6..0=0x13 + +#import zkne +$import rv32_zkne::aes32esmi +$import rv32_zkne::aes32esi + +#import zknd +# Scalar AES - RV32 +$import rv32_zknd::aes32dsmi +$import rv32_zknd::aes32dsi + + +#import zknh +# Scalar SHA512 - RV32 +$import rv32_zknh::sha512sum0r +$import rv32_zknh::sha512sum1r +$import rv32_zknh::sha512sig0l +$import rv32_zknh::sha512sig0h +$import rv32_zknh::sha512sig1l +$import rv32_zknh::sha512sig1h + diff --git a/rv32_zknd b/rv32_zknd new file mode 100644 index 0000000..f367d5e --- /dev/null +++ b/rv32_zknd @@ -0,0 +1,4 @@ +# Scalar AES - RV32 +aes32dsmi rd rs1 rs2 bs 29..25=0b10111 14..12=0 6..0=0x33 +aes32dsi rd rs1 rs2 bs 29..25=0b10101 14..12=0 6..0=0x33 + diff --git a/rv32_zkne b/rv32_zkne new file mode 100644 index 0000000..72bd617 --- /dev/null +++ b/rv32_zkne @@ -0,0 +1,5 @@ +# Scalar AES - RV32 + +aes32esmi rd rs1 rs2 bs 29..25=0b10011 14..12=0 6..0=0x33 +aes32esi rd rs1 rs2 bs 29..25=0b10001 14..12=0 6..0=0x33 + diff --git a/rv32_zknh b/rv32_zknh new file mode 100644 index 0000000..675bf54 --- /dev/null +++ b/rv32_zknh @@ -0,0 +1,8 @@ +# Scalar SHA512 - RV32 +sha512sum0r rd rs1 rs2 31..30=1 29..25=0b01000 14..12=0 6..0=0x33 +sha512sum1r rd rs1 rs2 31..30=1 29..25=0b01001 14..12=0 6..0=0x33 +sha512sig0l rd rs1 rs2 31..30=1 29..25=0b01010 14..12=0 6..0=0x33 +sha512sig0h rd rs1 rs2 31..30=1 29..25=0b01110 14..12=0 6..0=0x33 +sha512sig1l rd rs1 rs2 31..30=1 29..25=0b01011 14..12=0 6..0=0x33 +sha512sig1h rd rs1 rs2 31..30=1 29..25=0b01111 14..12=0 6..0=0x33 + diff --git a/rv32_zks b/rv32_zks new file mode 100644 index 0000000..034c532 --- /dev/null +++ b/rv32_zks @@ -0,0 +1,6 @@ +#import zbkb +$pseudo_op rv64_zbp::shfli zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=4 1..0=3 +$pseudo_op rv64_zbp::unshfli unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=4 1..0=3 +$pseudo_op rv64_zbb::rori rori rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x698 14..12=5 6..0=0x13 + diff --git a/rv64_zk b/rv64_zk new file mode 100644 index 0000000..0ebf71d --- /dev/null +++ b/rv64_zk @@ -0,0 +1,28 @@ +#import zbkb +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 +$import rv64_zbb::rolw +$import rv64_zbb::rorw +$import rv64_zbb::roriw +$import rv64_zbb::rori +$import rv64_zbe::packw + +#import zkne +# Scalar AES - RV64 +$import rv64_zkne::aes64esm +$import rv64_zkne::aes64es +$import rv64_zknd::aes64ks1i +$import rv64_zknd::aes64ks2 + +#import zknd +# Scalar AES - RV64 +$import rv64_zknd::aes64dsm +$import rv64_zknd::aes64ds +$import rv64_zknd::aes64im + +#import zknh +# Scalar SHA512 - RV64 +$import rv64_zknh::sha512sum0 +$import rv64_zknh::sha512sum1 +$import rv64_zknh::sha512sig0 +$import rv64_zknh::sha512sig1 + diff --git a/rv64_zkn b/rv64_zkn new file mode 100644 index 0000000..0ebf71d --- /dev/null +++ b/rv64_zkn @@ -0,0 +1,28 @@ +#import zbkb +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 +$import rv64_zbb::rolw +$import rv64_zbb::rorw +$import rv64_zbb::roriw +$import rv64_zbb::rori +$import rv64_zbe::packw + +#import zkne +# Scalar AES - RV64 +$import rv64_zkne::aes64esm +$import rv64_zkne::aes64es +$import rv64_zknd::aes64ks1i +$import rv64_zknd::aes64ks2 + +#import zknd +# Scalar AES - RV64 +$import rv64_zknd::aes64dsm +$import rv64_zknd::aes64ds +$import rv64_zknd::aes64im + +#import zknh +# Scalar SHA512 - RV64 +$import rv64_zknh::sha512sum0 +$import rv64_zknh::sha512sum1 +$import rv64_zknh::sha512sig0 +$import rv64_zknh::sha512sig1 + diff --git a/rv64_zknd b/rv64_zknd new file mode 100644 index 0000000..f1507d6 --- /dev/null +++ b/rv64_zknd @@ -0,0 +1,7 @@ +# Scalar AES - RV64 +aes64dsm rd rs1 rs2 31..30=0 29..25=0b11111 14..12=0b000 6..0=0x33 +aes64ds rd rs1 rs2 31..30=0 29..25=0b11101 14..12=0b000 6..0=0x33 +aes64ks1i rd rs1 rnum 31..30=0 29..25=0b11000 24=1 14..12=0b001 6..0=0x13 +aes64im rd rs1 31..30=0 29..25=0b11000 24..20=0b0000 14..12=0b001 6..0=0x13 +aes64ks2 rd rs1 rs2 31..30=1 29..25=0b11111 14..12=0b000 6..0=0x33 + diff --git a/rv64_zkne b/rv64_zkne new file mode 100644 index 0000000..3323b7f --- /dev/null +++ b/rv64_zkne @@ -0,0 +1,5 @@ +# Scalar AES - RV64 +aes64esm rd rs1 rs2 31..30=0 29..25=0b11011 14..12=0b000 6..0=0x33 +aes64es rd rs1 rs2 31..30=0 29..25=0b11001 14..12=0b000 6..0=0x33 +$import rv64_zknd::aes64ks1i +$import rv64_zknd::aes64ks2 diff --git a/rv64_zknh b/rv64_zknh new file mode 100644 index 0000000..431a1bc --- /dev/null +++ b/rv64_zknh @@ -0,0 +1,6 @@ +# Scalar SHA512 - RV64 +sha512sum0 rd rs1 31..30=0 29..25=0b01000 24..20=0b00100 14..12=1 6..0=0x13 +sha512sum1 rd rs1 31..30=0 29..25=0b01000 24..20=0b00101 14..12=1 6..0=0x13 +sha512sig0 rd rs1 31..30=0 29..25=0b01000 24..20=0b00110 14..12=1 6..0=0x13 +sha512sig1 rd rs1 31..30=0 29..25=0b01000 24..20=0b00111 14..12=1 6..0=0x13 + diff --git a/rv64_zks b/rv64_zks new file mode 100644 index 0000000..6bbad27 --- /dev/null +++ b/rv64_zks @@ -0,0 +1,7 @@ +#import zbkb +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 +$import rv64_zbb::rolw +$import rv64_zbb::rorw +$import rv64_zbb::roriw +$import rv64_zbb::rori +$import rv64_zbe::packw diff --git a/rv_zk b/rv_zk new file mode 100644 index 0000000..bdd8514 --- /dev/null +++ b/rv_zk @@ -0,0 +1,24 @@ +# import zbkb +$import rv_zbb::rol +$import rv_zbb::ror +$import rv_zbb::andn +$import rv_zbb::orn +$import rv_zbb::xnor +$import rv_zbe::pack +$import rv_zbe::packh +$pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 + +#import zbkc +$import rv_zbc::clmul +$import rv_zbc::clmulh + +#import zbkx +$import rv_zbkx::xperm4 +$import rv_zbkx::xperm8 + +#import zknh +# Scalar SHA256 - RV32/RV64 +$import rv_zknh::sha256sum0 +$import rv_zknh::sha256sum1 +$import rv_zknh::sha256sig0 +$import rv_zknh::sha256sig1 diff --git a/rv_zkn b/rv_zkn new file mode 100644 index 0000000..bdd8514 --- /dev/null +++ b/rv_zkn @@ -0,0 +1,24 @@ +# import zbkb +$import rv_zbb::rol +$import rv_zbb::ror +$import rv_zbb::andn +$import rv_zbb::orn +$import rv_zbb::xnor +$import rv_zbe::pack +$import rv_zbe::packh +$pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 + +#import zbkc +$import rv_zbc::clmul +$import rv_zbc::clmulh + +#import zbkx +$import rv_zbkx::xperm4 +$import rv_zbkx::xperm8 + +#import zknh +# Scalar SHA256 - RV32/RV64 +$import rv_zknh::sha256sum0 +$import rv_zknh::sha256sum1 +$import rv_zknh::sha256sig0 +$import rv_zknh::sha256sig1 diff --git a/rv_zknh b/rv_zknh new file mode 100644 index 0000000..2079628 --- /dev/null +++ b/rv_zknh @@ -0,0 +1,5 @@ +# Scalar SHA256 - RV32/RV64 +sha256sum0 rd rs1 31..30=0 29..25=0b01000 24..20=0b00000 14..12=1 6..0=0x13 +sha256sum1 rd rs1 31..30=0 29..25=0b01000 24..20=0b00001 14..12=1 6..0=0x13 +sha256sig0 rd rs1 31..30=0 29..25=0b01000 24..20=0b00010 14..12=1 6..0=0x13 +sha256sig1 rd rs1 31..30=0 29..25=0b01000 24..20=0b00011 14..12=1 6..0=0x13 diff --git a/rv_zks b/rv_zks new file mode 100644 index 0000000..20516f3 --- /dev/null +++ b/rv_zks @@ -0,0 +1,26 @@ +# import zbkb +$import rv_zbb::rol +$import rv_zbb::ror +$import rv_zbb::andn +$import rv_zbb::orn +$import rv_zbb::xnor +$import rv_zbe::pack +$import rv_zbe::packh +$pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 + +#import zbkc +$import rv_zbc::clmul +$import rv_zbc::clmulh + +#import zbkx +$import rv_zbkx::xperm4 +$import rv_zbkx::xperm8 + +# Scalar SM4 - RV32, RV64 +$import rv_zksed::sm4ed +$import rv_zksed::sm4ks + +# Scalar SM3 - RV32, RV64 +$import rv_zksh::sm3p0 +$import rv_zksh::sm3p1 + diff --git a/rv_zksed b/rv_zksed new file mode 100644 index 0000000..92e17c5 --- /dev/null +++ b/rv_zksed @@ -0,0 +1,4 @@ +# Scalar SM4 - RV32, RV64 +sm4ed rd rs1 rs2 bs 29..25=0b11000 14..12=0 6..0=0x33 +sm4ks rd rs1 rs2 bs 29..25=0b11010 14..12=0 6..0=0x33 + diff --git a/rv_zksh b/rv_zksh new file mode 100644 index 0000000..f21eaa8 --- /dev/null +++ b/rv_zksh @@ -0,0 +1,4 @@ +# Scalar SM3 - RV32, RV64 +sm3p0 rd rs1 31..30=0 29..25=0b01000 24..20=0b01000 14..12=1 6..0=0x13 +sm3p1 rd rs1 31..30=0 29..25=0b01000 24..20=0b01001 14..12=1 6..0=0x13 + -- cgit v1.1 From dc03fedb066c80228518d6ecb943abe92a21b11c Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 19:18:24 +0530 Subject: migrating Zbkc-Extension opcodes --- rv_zbkc | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 rv_zbkc diff --git a/rv_zbkc b/rv_zbkc new file mode 100644 index 0000000..b82588f --- /dev/null +++ b/rv_zbkc @@ -0,0 +1,2 @@ +$import rv_zbc::clmul +$import rv_zbc::clmulh -- cgit v1.1 From 80959a74a4500468fd99aa053f582a62097ccd93 Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 19:30:47 +0530 Subject: migrate unratified and uncategorized bitmanip ops --- unratified/rv64_b | 9 +++++++++ unratified/rv_b | 12 ++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 unratified/rv64_b create mode 100644 unratified/rv_b diff --git a/unratified/rv64_b b/unratified/rv64_b new file mode 100644 index 0000000..3d01b8c --- /dev/null +++ b/unratified/rv64_b @@ -0,0 +1,9 @@ +# RV64B additions to RV32B + + +slow rd rs1 rs2 31..25=16 14..12=1 6..2=0x0E 1..0=3 +srow rd rs1 rs2 31..25=16 14..12=5 6..2=0x0E 1..0=3 + +sloiw rd rs1 31..26=8 25=0 shamtw 14..12=1 6..2=0x06 1..0=3 +sroiw rd rs1 31..26=8 25=0 shamtw 14..12=5 6..2=0x06 1..0=3 + diff --git a/unratified/rv_b b/unratified/rv_b new file mode 100644 index 0000000..4fe7ef0 --- /dev/null +++ b/unratified/rv_b @@ -0,0 +1,12 @@ + +slo rd rs1 rs2 31..25=16 14..12=1 6..2=0x0C 1..0=3 +sro rd rs1 rs2 31..25=16 14..12=5 6..2=0x0C 1..0=3 + + +sloi rd rs1 31..26=8 shamt 14..12=1 6..2=0x04 1..0=3 +sroi rd rs1 31..26=8 shamt 14..12=5 6..2=0x04 1..0=3 + + + + + -- cgit v1.1 From d048be03c066edcd30fa24cad8528b6ff35ea90a Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 19:55:22 +0530 Subject: fix import of pseudo op for fsri - pseudo ops cannot be imported. The pseudo_op syntax itself should be used where applicable. --- unratified/rv32_zbpbo | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/unratified/rv32_zbpbo b/unratified/rv32_zbpbo index 6ecc566..e5c296f 100644 --- a/unratified/rv32_zbpbo +++ b/unratified/rv32_zbpbo @@ -1,5 +1,5 @@ $import rv_zbb::clz $import rv_zbt::fsr -$import rv32_zbt::fsri +$pseudo_op rv64_zbt::fsri fsri rd rs1 rs3 26=1 25=0 shamtw 14..12=5 6..2=0x04 1..0=3 $pseudo_op rv64_zbp::grevi rev rd rs1 31..20=0x69F 14..12=5 6..0=0x13 -- cgit v1.1 From 8b01b9489f19d047d5033fa6dacfe8524123462b Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 20:47:02 +0530 Subject: moving pseudo_ops in opcode-pseudo to relevant extension files --- opcodes-pseudo | 32 -------------------------------- rv_f | 5 +++++ rv_i | 8 ++++++++ rv_zicsr | 16 ++++++++++++++++ 4 files changed, 29 insertions(+), 32 deletions(-) delete mode 100644 opcodes-pseudo diff --git a/opcodes-pseudo b/opcodes-pseudo deleted file mode 100644 index 2cd7c91..0000000 --- a/opcodes-pseudo +++ /dev/null @@ -1,32 +0,0 @@ -# Instructions that differ slightly between rv32 and rv64 -@slli.rv32 rd rs1 31..25=0 shamtw 14..12=1 6..2=0x04 1..0=3 -@srli.rv32 rd rs1 31..25=0 shamtw 14..12=5 6..2=0x04 1..0=3 -@srai.rv32 rd rs1 31..25=32 shamtw 14..12=5 6..2=0x04 1..0=3 - -# SYSTEM pseudo-instructions that map to csr* -@frflags rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3 -@fsflags rd rs1 31..20=0x001 14..12=1 6..2=0x1C 1..0=3 -@fsflagsi rd zimm 31..20=0x001 14..12=5 6..2=0x1C 1..0=3 -@frrm rd 19..15=0 31..20=0x002 14..12=2 6..2=0x1C 1..0=3 -@fsrm rd rs1 31..20=0x002 14..12=1 6..2=0x1C 1..0=3 -@fsrmi rd zimm 31..20=0x002 14..12=5 6..2=0x1C 1..0=3 -@fscsr rd rs1 31..20=0x003 14..12=1 6..2=0x1C 1..0=3 -@frcsr rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3 -@rdcycle rd 19..15=0 31..20=0xC00 14..12=2 6..2=0x1C 1..0=3 -@rdtime rd 19..15=0 31..20=0xC01 14..12=2 6..2=0x1C 1..0=3 -@rdinstret rd 19..15=0 31..20=0xC02 14..12=2 6..2=0x1C 1..0=3 -@rdcycleh rd 19..15=0 31..20=0xC80 14..12=2 6..2=0x1C 1..0=3 -@rdtimeh rd 19..15=0 31..20=0xC81 14..12=2 6..2=0x1C 1..0=3 -@rdinstreth rd 19..15=0 31..20=0xC82 14..12=2 6..2=0x1C 1..0=3 - -# Old names for ecall/ebreak -@scall 11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3 -@sbreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3 - -# Old names for fmv.x.w/fmv.w.x -@fmv.x.s rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3 -@fmv.s.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 - -# specialized fences -@fence.tso 31..28=8 27..24=3 23..20=3 19..15=ignore 14..12=0 11..7=ignore 6..2=0x03 1..0=3 -@pause 31..28=0 27..24=1 23..20=0 19..15=0 14..12=0 11..7=0 6..2=0x03 1..0=3 diff --git a/rv_f b/rv_f index c148dd2..d94547b 100644 --- a/rv_f +++ b/rv_f @@ -24,3 +24,8 @@ fclass.s rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=0 6..2=0x14 1..0=3 fcvt.s.w rd rs1 24..20=0 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 fcvt.s.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 fmv.w.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 + +#Old names for fmv.x.w/fmv.w.x +$pseudo_op rv_f::fmv.x.w fmv.x.s rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3 +$pseudo_op rv_f::fmv.w.x fmv.s.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 + diff --git a/rv_i b/rv_i index 8b1569a..fc27403 100644 --- a/rv_i +++ b/rv_i @@ -35,5 +35,13 @@ sra rd rs1 rs2 31..25=32 14..12=5 6..2=0x0C 1..0=3 or rd rs1 rs2 31..25=0 14..12=6 6..2=0x0C 1..0=3 and rd rs1 rs2 31..25=0 14..12=7 6..2=0x0C 1..0=3 fence fm pred succ rs1 14..12=0 rd 6..2=0x03 1..0=3 +#specialized fences +$pseudo_op rv_i::fence fence.tso 31..28=8 27..24=3 23..20=3 19..15=0 14..12=0 11..7=0 6..2=0x03 1..0=3 +$pseudo_op rv_i::fence pause 31..28=0 27..24=1 23..20=0 19..15=0 14..12=0 11..7=0 6..2=0x03 1..0=3 ecall 31..20=0x000 19..7=0 6..2=0x1C 1..0=3 ebreak 31..20=0x001 19..7=0 6..2=0x1C 1..0=3 + +#Old names for ecall/ebreak +$pseudo_op rv_i::ecall scall 11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3 +$pseudo_op rv_i::ebreak sbreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3 + diff --git a/rv_zicsr b/rv_zicsr index 5c3e338..c58b5bd 100644 --- a/rv_zicsr +++ b/rv_zicsr @@ -5,3 +5,19 @@ csrrwi rd csr zimm 14..12=5 6..2=0x1C 1..0=3 csrrsi rd csr zimm 14..12=6 6..2=0x1C 1..0=3 csrrci rd csr zimm 14..12=7 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs frflags rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw fsflags rd rs1 31..20=0x001 14..12=1 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrwi fsflagsi rd zimm 31..20=0x001 14..12=5 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs frrm rd 19..15=0 31..20=0x002 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw fsrm rd rs1 31..20=0x002 14..12=1 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrwi fsrmi rd zimm 31..20=0x002 14..12=5 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw fscsr rd rs1 31..20=0x003 14..12=1 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs frcsr rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs rdcycle rd 19..15=0 31..20=0xC00 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs rdtime rd 19..15=0 31..20=0xC01 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs rdinstret rd 19..15=0 31..20=0xC02 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs rdcycleh rd 19..15=0 31..20=0xC80 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs rdtimeh rd 19..15=0 31..20=0xC81 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs rdinstreth rd 19..15=0 31..20=0xC82 14..12=2 6..2=0x1C 1..0=3 + + -- cgit v1.1 From bd26319a75b2ae4f52dc397b22c97e19b08d527f Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 20:51:52 +0530 Subject: updated python script, Makefile and README to process new files - the python file is well commented - the README provides a brief overview of how the python script works and the various artifacts it can generate --- .gitignore | 7 + Makefile | 55 ++- README.md | 203 +++++++++- constants.py | 597 +++++++++++++++++++++++++++ parse.py | 872 ++++++++++++++++++++++++++++++++++++++++ parse_opcodes | 1240 --------------------------------------------------------- 6 files changed, 1700 insertions(+), 1274 deletions(-) create mode 100644 constants.py create mode 100755 parse.py delete mode 100755 parse_opcodes diff --git a/.gitignore b/.gitignore index ccff222..406d882 100644 --- a/.gitignore +++ b/.gitignore @@ -4,3 +4,10 @@ inst.chisel inst.go instr-table.tex priv-instr-table.tex +inst.rs + +inst.sverilog + +instr_dict.yaml + +__pycache__/ diff --git a/Makefile b/Makefile index 6354ecc..828916f 100644 --- a/Makefile +++ b/Makefile @@ -1,44 +1,41 @@ -SHELL := /bin/sh - +EXTENSIONS := "rv*" "unratified/rv*" ISASIM_H := ../riscv-isa-sim/riscv/encoding.h PK_H := ../riscv-pk/machine/encoding.h ENV_H := ../riscv-tests/env/encoding.h OPENOCD_H := ../riscv-openocd/src/target/riscv/encoding.h INSTALL_HEADER_FILES := $(ISASIM_H) $(PK_H) $(ENV_H) $(OPENOCD_H) -ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32h opcodes-rv64h opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-rv32xbitmanip opcodes-rv64xbitmanip opcodes-system opcodes-svinval opcodes-rv32zfh opcodes-rv32d-zfh opcodes-rv32q-zfh opcodes-rv64zfh opcodes-rvzk opcodes-rv32zk opcodes-rv64zk opcodes-zicbo opcodes-rv32zba opcodes-rv32zbb opcodes-rv32zbc opcodes-rv32zbkb opcodes-rv32zbkx opcodes-rv32zbs opcodes-rv64zba opcodes-rv64zbb opcodes-rv64zbkb -ALL_REAL_OPCODES := $(ALL_REAL_ILEN32_OPCODES) opcodes-rvc opcodes-rv32c opcodes-rv64c opcodes-custom opcodes-rvv opcodes-rvp - -ALL_OPCODES := opcodes-pseudo $(ALL_REAL_OPCODES) opcodes-rvv-pseudo - -install: encoding.out.h inst.chisel instr-table.tex priv-instr-table.tex - set -e; for FILE in $(INSTALL_HEADER_FILES); do cp -f encoding.out.h $$FILE; done +default: everything -encoding.out.h: $(ALL_OPCODES) parse_opcodes encoding.h - echo "/*" > $@ - echo " * This file is auto-generated by running 'make' in" >> $@ - echo " * https://github.com/riscv/riscv-opcodes (`git log -1 --format="format:%h"`)" >> $@ - echo " */" >> $@ - echo >> $@ - cat encoding.h >> $@ - cat $(ALL_OPCODES) | ./parse_opcodes -c >> $@ +.PHONY : everything +everything: + @./parse.py -c -chisel -sverilog -rust -latex $(EXTENSIONS) -inst.chisel: $(ALL_OPCODES) parse_opcodes - cat $(ALL_OPCODES) | ./parse_opcodes -chisel > $@ +.PHONY : c +c: + @./parse.py -c $(EXTENSIONS) -inst.go: $(ALL_REAL_ILEN32_OPCODES) parse_opcodes - cat $(ALL_REAL_ILEN32_OPCODES) | ./parse_opcodes -go > $@ +.PHONY : chisel +chisel: + @./parse.py -chisel $(EXTENSIONS) -inst.rs: $(ALL_OPCODES) parse_opcodes - cat $(ALL_OPCODES) | ./parse_opcodes -rust > $@ +.PHONY : latex +latex: + @./parse.py -latex $(EXTENSIONS) -inst.sverilog: $(ALL_OPCODES) parse_opcodes - cat $(ALL_OPCODES) | ./parse_opcodes -sverilog > $@ +.PHONY : sverilog +sverilog: + @./parse.py -sverilog $(EXTENSIONS) -instr-table.tex: $(ALL_OPCODES) parse_opcodes - cat $(ALL_OPCODES) | ./parse_opcodes -tex > $@ +.PHONY : rust +rust: + @./parse.py -rust $(EXTENSIONS) -priv-instr-table.tex: $(ALL_OPCODES) parse_opcodes - cat $(ALL_OPCODES) | ./parse_opcodes -privtex > $@ +.PHONY : clean +clean: + rm -f inst* priv-instr-table.tex encoding.out.h .PHONY : install +install: c + set -e; for FILE in $(INSTALL_HEADER_FILES); do cp -f encoding.out.h $$FILE; done + diff --git a/README.md b/README.md index bb981ea..26d39fc 100644 --- a/README.md +++ b/README.md @@ -1,10 +1,203 @@ -riscv-opcodes -=========================================================================== +# riscv-opcodes This repo enumerates standard RISC-V instruction opcodes and control and status registers. It also contains a script to convert them into several formats (C, Scala, LaTeX). -This repo is not meant to stand alone; it is a subcomponent of -[riscv-tools](https://github.com/riscv/riscv-tools) and assumes that it -is part of that directory structure. +Artifacts (encoding.h, latex-tables, etc) from this repo are used in other +tools and projects like Spike, PK, RISC-V Manual, etc. + +## Project Structure + +```bash +├── constants.py # contains variables, constants and data-structures used in parse.py +├── encoding.h # the template encoding.h file +├── LICENSE # license file +├── Makefile # makefile to generate artifacts +├── parse.py # python file to perform checks on the instructions and generate artifacts +├── README.md # this file +├── rv* # instruction opcode files +└── unratified # contains unratified instruction opcode files +``` + +## File Naming Policy + +This project follows a very specific file structure to define the instruction encodings. All files +containing instruction encodings start with the prefix `rv`. These files can either be present in +the root directory (if the instructions have been ratified) of the `unratified` directory. The exact +file-naming policy and location is as mentioned below: + +1. `rv_x` - contains instructions common within the 32-bit and 64-bit modes of extension X. +2. `rv32_x` - contains instructions present in rv32x only (absent in rv64x e.g.. brev8) +3. `rv64_x` - contains instructions present in rv64x only (absent in rv32x, e.g. addw) +4. `rv_x_y` - contains instructions when both extension X and Y are available/enabled. It is recommended to follow canonical ordering for such file names as specified by the spec. +5. `unratified` - this directory will also contain files similar to the above policies, but will + correspond to instructions which have not yet been ratified. + +When an instruction is present in multiple extensions and the spec is vague in defining the extension which owns the instruction, the instruction encoding must be placed in the first canonically ordered extension and should be imported(via the `$import` keyword) in the remaining extensions. + +## Encoding Syntax + + +The encoding syntax uses `$` to indicate keywords. As of now 2 keywords have been identified : `$import` and `$pseudo_op` (described below). The syntax also uses `::` as a means to define the relationship between extension and instruction. `..` is used to defined bit ranges. We use `#` to define comments in the files. All comments must be in a separate line. In-line comments are not supported. + +Instruction syntaxes used in this project are broadly categorized into three: + +- **regular instructions** :- these are instructions which hold a unique opcode in the encoding space. A very generic syntax guideline + for these instructions is as follows: + ``` + + ``` + Examples: + ``` + lui rd imm20 6..2=0x0D 1..0=3 + beq bimm12hi rs1 rs2 bimm12lo 14..12=0 6..2=0x18 1..0=3 + ``` + The bit encodings are usually of 2 types: + - *single bit assignment* : here the value of a single bit is assigned using syntax `=`. For e.g. `6=1` means bit 6 should be 1. Here the value must be 1 or 0. + - *range assignment*: here a range of bits is assigned a value using syntax: `..=`. For e.g. `31..24=0xab`. The value here can be either unsigned integer, hex (0x) or binary (0b). + +- **pseudo\_instructions** (a.k.a pseudo\_ops) - These are instructions which are aliases of regular instructions. Their encodings force + certain restrictions over the regular instruction. The syntax for such instructions uses the `$pseudo_op` keyword as follows: + ``` + $pseudo_op :: + ``` + Here the `` specifies the extension which contains the base instruction. `` indicates the name of the instruction + this pseudo-instruction is an alias of. The remaining fields are the same as the regular instruction syntax, where all the args and the fields + of the pseudo instruction are specified. + + Example: + ``` + $pseudo_op rv_zicsr::csrrs frflags rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3 + ``` + + If a ratified instruction is a pseudo\_op of a regular unratified + instruction, it is recommended to maintain this pseudo\_op relationship i.e. + define the new instruction as a pseudo\_op of the unratified regular + instruction, as this avoids existence of overlapping opcodes for users who are + experimenting with unratified extensions as well. + +- **imported\_instructions** - these are instructions which are borrowed from an extension into a new/different extension/sub-extension. Only regular instructions can be imported. Pseudo-op instructions cannot be imported. Example: + ``` + $import rv32_zkne::aes32esmi + ``` +## Flow for parse.py + +The `parse.py` python file is used to perform checks on the current set of instruction encodings and also generates multiple artifacts : latex tables, encoding.h header file, etc. This section will provide a brief overview of the flow within the python file. + +To start with, `parse.py` creates a list of all `rv*` files currently checked into the repo (including those inside the `unratified` directory as well). +It then starts parsing each file line by line. In the first pass, we only capture regular instructions and ignore the imported or pseudo instructions. +For each regular instruction, the following checks are performed : + + - for range-assignment syntax, the *msb* position must be higher than the *lsb* position + - for range-assignment syntax, the value of the range must representable in the space identified by *msb* and *lsb* + - values for the same bit positions should not be defined multiple times. + - All bit positions must be accounted for (either as args or constant value fields) + +Once the above checks are passed for a regular instruction, we then create a dictionary for this instruction which contains the following fields: + - encoding : contains a 32-bit string defining the encoding of the instruction. Here `-` is used to represent instruction argument fields + - extension : string indicating which extension/filename this instruction was picked from + - mask : a 32-bit hex value indicating the bits of the encodings that must be checked for legality of that instruction + - match : a 32-bit hex value indicating the values the encoding must take for the bits which are set as 1 in the mask above + - variable_fields : This is list of args required by the instruction + +The above dictionary elements are added to a main `instr_dict` dictionary under the instruction node. This process continues until all regular +instructions have been processed. In the second pass, we now process the `$pseudo_op` instructions. Here, we first check if the *base-instruction* of +this pseudo instruction exists in the relevant extension/filename or not. If it is present, the the remaining part of the syntax undergoes the same +checks as above. Once the checks pass and if the *base-instruction* is not already added to the main `instr_dict` then the pseudo-instruction is added to +the list. In the third, and final, pass we process the imported instructions. + +The case where the *base-instruction* for a pseudo-instruction may not be present in the main `instr_dict` after the first pass is if the only a subset +of extensions are being processed such that the *base-instruction* is not included. + + +## Artifact Generation and Usage + +The following artifacts can be generated using parse.py: + +- instr\_dict.yaml : This is file generated always by parse.py and contains the + entire main dictionary `instr_dict` in YAML format. Note, in this yaml the + *dots* in an instruction are replaced with *underscores* +- encoding.h : this is the header file that is used by tools like spike, pk, etc +- instr-table.tex : the latex table of instructions used in the riscv-unpriv spec +- priv-instr-table.tex : the latex table of instruction used in the riscv-priv spec +- inst.chisel : chisel code to decode instructions +- inst.sverilog : system verilog code to decode instructions +- inst.rs : rust code containing mask and match variables for all instructions + +To generate all the above artifacts for all instructions currently checked in, simply run `make` from the root-directory. This should print the following log on the command-line: + +``` +Running with args : ['./parse.py', '-c', '-chisel', '-sverilog', '-rust', '-latex', 'rv*', 'unratified/rv*'] +Extensions selected : ['rv*', 'unratified/rv*'] +INFO:: encoding.out.h generated successfully +INFO:: inst.chisel generated successfully +INFO:: inst.sverilog generated successfully +INFO:: inst.rs generated successfully +INFO:: instr-table.tex generated successfully +INFO:: priv-instr-table.tex generated successfully +``` + +By default all extensions are enabled. To select only a subset of extensions you can change the `EXTENSIONS` variable of the makefile to contains only the file names of interest. +For example if you want only the I and M extensions you can do the following: + +```bash +make EXTENSIONS='rv*_i rv*_m' +``` + +Which will print the following log: + +``` +Running with args : ['./parse.py', '-c', '-chisel', '-sverilog', '-rust', '-latex', 'rv32_i', 'rv64_i', 'rv_i', 'rv64_m', 'rv_m'] +Extensions selected : ['rv32_i', 'rv64_i', 'rv_i', 'rv64_m', 'rv_m'] +INFO:: encoding.out.h generated successfully +INFO:: inst.chisel generated successfully +INFO:: inst.sverilog generated successfully +INFO:: inst.rs generated successfully +INFO:: instr-table.tex generated successfully +INFO:: priv-instr-table.tex generated successfully +``` + +If you only want a specific artifact you can use one or more of the following targets : `c`, `rust`, `chisel`, `sverilog`, `latex` + +You can use the `clean` target to remove all artifacts. + +## Adding a new extension + +To add a new extension of instructions, create an appropriate `rv*` file based on the policy defined in [File Structure](#file-naming-policy). Run `make` from the root directory to ensure that all checks pass and all artifacts are created correctly. A successful run should print the following log on the terminal: + +``` +Running with args : ['./parse.py', '-c', '-chisel', '-sverilog', '-rust', '-latex', 'rv*', 'unratified/rv*'] +Extensions selected : ['rv*', 'unratified/rv*'] +INFO:: encoding.out.h generated successfully +INFO:: inst.chisel generated successfully +INFO:: inst.sverilog generated successfully +INFO:: inst.rs generated successfully +INFO:: instr-table.tex generated successfully +INFO:: priv-instr-table.tex generated successfully +``` + +Create a PR for review. + +## Enabling Debug logs in parse.py + +To enable debug logs in parse.py change `level=logging.INFO` to `level=logging.DEBUG` and run the python command. You will now see debug statements on +the terminal like below: +``` +DEBUG:: Collecting standard instructions first +DEBUG:: Parsing File: ./rv_i +DEBUG:: Processing line: lui rd imm20 6..2=0x0D 1..0=3 +DEBUG:: Processing line: auipc rd imm20 6..2=0x05 1..0=3 +DEBUG:: Processing line: jal rd jimm20 6..2=0x1b 1..0=3 +DEBUG:: Processing line: jalr rd rs1 imm12 14..12=0 6..2=0x19 1..0=3 +DEBUG:: Processing line: beq bimm12hi rs1 rs2 bimm12lo 14..12=0 6..2=0x18 1..0=3 +DEBUG:: Processing line: bne bimm12hi rs1 rs2 bimm12lo 14..12=1 6..2=0x18 1..0=3 +``` + +## How do I find where an instruction is defined? + +You can use `grep "^\s*" rv* unratified/rv*` OR run `make` and open +`instr_dict.yaml` and search of the instruction you are looking for. Within that +instruction the `extension` field will indicate which file the instruction was +picked from. + diff --git a/constants.py b/constants.py new file mode 100644 index 0000000..b6a4351 --- /dev/null +++ b/constants.py @@ -0,0 +1,597 @@ +import re + + +isa_regex = \ +re.compile("^RV(32|64|128)[IE]+[ABCDEFGHJKLMNPQSTUVX]*(Zicsr|Zifencei|Zihintpause|Zam|Ztso|Zkne|Zknd|Zknh|Zkse|Zksh|Zkg|Zkb|Zkr|Zks|Zkn|Zba|Zbc|Zbb|Zbp|Zbr|Zbm|Zbs|Zbe|Zbf|Zbt|Zmmul|Zbpbo){,1}(_Zicsr){,1}(_Zifencei){,1}(_Zihintpause){,1}(_Zmmul){,1}(_Zam){,1}(_Zba){,1}(_Zbb){,1}(_Zbc){,1}(_Zbe){,1}(_Zbf){,1}(_Zbm){,1}(_Zbp){,1}(_Zbpbo){,1}(_Zbr){,1}(_Zbs){,1}(_Zbt){,1}(_Zkb){,1}(_Zkg){,1}(_Zkr){,1}(_Zks){,1}(_Zkn){,1}(_Zknd){,1}(_Zkne){,1}(_Zknh){,1}(_Zkse){,1}(_Zksh){,1}(_Ztso){,1}$") + +# regex to find ..= patterns in instruction +fixed_ranges = re.compile( + '\s*(?P\d+.?)\.\.(?P\d+.?)\s*=\s*(?P\d[\w]*)[\s$]*', re.M) + +# regex to find = patterns in instructions +#single_fixed = re.compile('\s+(?P\d+)=(?P[\w\d]*)[\s$]*', re.M) +single_fixed = re.compile('(?:^|[\s])(?P\d+)=(?P[\w]*)((?=\s|$))', re.M) + +# regex to find the overloading condition variable +var_regex = re.compile('(?P[a-zA-Z][\w\d]*)\s*=\s*.*?[\s$]*', re.M) + +# regex for pseudo op instructions returns the dependent filename, dependent +# instruction, the pseudo op name and the encoding string +pseudo_regex = re.compile( + '^\$pseudo_op\s+(?Prv[\d]*_[\w].*)::\s*(?P.*?)\s+(?P.*?)\s+(?P.*)$' +, re.M) + +imported_regex = re.compile('^\s*\$import\s*(?P.*)\s*::\s*(?P.*)', re.M) + +# +# Trap cause codes +causes = [ + (0x00, 'misaligned fetch'), + (0x01, 'fetch access'), + (0x02, 'illegal instruction'), + (0x03, 'breakpoint'), + (0x04, 'misaligned load'), + (0x05, 'load access'), + (0x06, 'misaligned store'), + (0x07, 'store access'), + (0x08, 'user_ecall'), + (0x09, 'supervisor_ecall'), + (0x0A, 'virtual_supervisor_ecall'), + (0x0B, 'machine_ecall'), + (0x0C, 'fetch page fault'), + (0x0D, 'load page fault'), + (0x0F, 'store page fault'), + (0x14, 'fetch guest page fault'), + (0x15, 'load guest page fault'), + (0x16, 'virtual instruction'), + (0x17, 'store guest page fault'), +] + +csrs = [ + # Standard User R/W + (0x001, 'fflags'), + (0x002, 'frm'), + (0x003, 'fcsr'), + (0x008, 'vstart'), + (0x009, 'vxsat'), + (0x00A, 'vxrm'), + (0x00F, 'vcsr'), + (0x015, 'seed'), # Zkr + + # Standard User RO + (0xC00, 'cycle'), + (0xC01, 'time'), + (0xC02, 'instret'), + (0xC03, 'hpmcounter3'), + (0xC04, 'hpmcounter4'), + (0xC05, 'hpmcounter5'), + (0xC06, 'hpmcounter6'), + (0xC07, 'hpmcounter7'), + (0xC08, 'hpmcounter8'), + (0xC09, 'hpmcounter9'), + (0xC0A, 'hpmcounter10'), + (0xC0B, 'hpmcounter11'), + (0xC0C, 'hpmcounter12'), + (0xC0D, 'hpmcounter13'), + (0xC0E, 'hpmcounter14'), + (0xC0F, 'hpmcounter15'), + (0xC10, 'hpmcounter16'), + (0xC11, 'hpmcounter17'), + (0xC12, 'hpmcounter18'), + (0xC13, 'hpmcounter19'), + (0xC14, 'hpmcounter20'), + (0xC15, 'hpmcounter21'), + (0xC16, 'hpmcounter22'), + (0xC17, 'hpmcounter23'), + (0xC18, 'hpmcounter24'), + (0xC19, 'hpmcounter25'), + (0xC1A, 'hpmcounter26'), + (0xC1B, 'hpmcounter27'), + (0xC1C, 'hpmcounter28'), + (0xC1D, 'hpmcounter29'), + (0xC1E, 'hpmcounter30'), + (0xC1F, 'hpmcounter31'), + (0xC20, 'vl'), + (0xC21, 'vtype'), + (0xC22, 'vlenb'), + + # Standard Supervisor R/W + (0x100, 'sstatus'), + (0x102, 'sedeleg'), + (0x103, 'sideleg'), + (0x104, 'sie'), + (0x105, 'stvec'), + (0x106, 'scounteren'), + (0x10A, 'senvcfg'), + (0x140, 'sscratch'), + (0x141, 'sepc'), + (0x142, 'scause'), + (0x143, 'stval'), + (0x144, 'sip'), + (0x180, 'satp'), + (0x5A8, 'scontext'), + + # Standard Hypervisor R/w + (0x200, 'vsstatus'), + (0x204, 'vsie'), + (0x205, 'vstvec'), + (0x240, 'vsscratch'), + (0x241, 'vsepc'), + (0x242, 'vscause'), + (0x243, 'vstval'), + (0x244, 'vsip'), + (0x280, 'vsatp'), + (0x600, 'hstatus'), + (0x602, 'hedeleg'), + (0x603, 'hideleg'), + (0x604, 'hie'), + (0x605, 'htimedelta'), + (0x606, 'hcounteren'), + (0x607, 'hgeie'), + (0x60A, 'henvcfg'), + (0x643, 'htval'), + (0x644, 'hip'), + (0x645, 'hvip'), + (0x64A, 'htinst'), + (0x680, 'hgatp'), + (0x6A8, 'hcontext'), + (0xE12, 'hgeip'), + + # Tentative CSR assignment for CLIC + (0x007, 'utvt'), + (0x045, 'unxti'), + (0x046, 'uintstatus'), + (0x048, 'uscratchcsw'), + (0x049, 'uscratchcswl'), + (0x107, 'stvt'), + (0x145, 'snxti'), + (0x146, 'sintstatus'), + (0x148, 'sscratchcsw'), + (0x149, 'sscratchcswl'), + (0x307, 'mtvt'), + (0x345, 'mnxti'), + (0x346, 'mintstatus'), + (0x348, 'mscratchcsw'), + (0x349, 'mscratchcswl'), + + # Standard Machine R/W + (0x300, 'mstatus'), + (0x301, 'misa'), + (0x302, 'medeleg'), + (0x303, 'mideleg'), + (0x304, 'mie'), + (0x305, 'mtvec'), + (0x306, 'mcounteren'), + (0x30a, 'menvcfg'), + (0x320, 'mcountinhibit'), + (0x340, 'mscratch'), + (0x341, 'mepc'), + (0x342, 'mcause'), + (0x343, 'mtval'), + (0x344, 'mip'), + (0x34a, 'mtinst'), + (0x34b, 'mtval2'), + (0x3a0, 'pmpcfg0'), + (0x3a1, 'pmpcfg1'), + (0x3a2, 'pmpcfg2'), + (0x3a3, 'pmpcfg3'), + (0x3a4, 'pmpcfg4'), + (0x3a5, 'pmpcfg5'), + (0x3a6, 'pmpcfg6'), + (0x3a7, 'pmpcfg7'), + (0x3a8, 'pmpcfg8'), + (0x3a9, 'pmpcfg9'), + (0x3aa, 'pmpcfg10'), + (0x3ab, 'pmpcfg11'), + (0x3ac, 'pmpcfg12'), + (0x3ad, 'pmpcfg13'), + (0x3ae, 'pmpcfg14'), + (0x3af, 'pmpcfg15'), + (0x3b0, 'pmpaddr0'), + (0x3b1, 'pmpaddr1'), + (0x3b2, 'pmpaddr2'), + (0x3b3, 'pmpaddr3'), + (0x3b4, 'pmpaddr4'), + (0x3b5, 'pmpaddr5'), + (0x3b6, 'pmpaddr6'), + (0x3b7, 'pmpaddr7'), + (0x3b8, 'pmpaddr8'), + (0x3b9, 'pmpaddr9'), + (0x3ba, 'pmpaddr10'), + (0x3bb, 'pmpaddr11'), + (0x3bc, 'pmpaddr12'), + (0x3bd, 'pmpaddr13'), + (0x3be, 'pmpaddr14'), + (0x3bf, 'pmpaddr15'), + (0x3c0, 'pmpaddr16'), + (0x3c1, 'pmpaddr17'), + (0x3c2, 'pmpaddr18'), + (0x3c3, 'pmpaddr19'), + (0x3c4, 'pmpaddr20'), + (0x3c5, 'pmpaddr21'), + (0x3c6, 'pmpaddr22'), + (0x3c7, 'pmpaddr23'), + (0x3c8, 'pmpaddr24'), + (0x3c9, 'pmpaddr25'), + (0x3ca, 'pmpaddr26'), + (0x3cb, 'pmpaddr27'), + (0x3cc, 'pmpaddr28'), + (0x3cd, 'pmpaddr29'), + (0x3ce, 'pmpaddr30'), + (0x3cf, 'pmpaddr31'), + (0x3d0, 'pmpaddr32'), + (0x3d1, 'pmpaddr33'), + (0x3d2, 'pmpaddr34'), + (0x3d3, 'pmpaddr35'), + (0x3d4, 'pmpaddr36'), + (0x3d5, 'pmpaddr37'), + (0x3d6, 'pmpaddr38'), + (0x3d7, 'pmpaddr39'), + (0x3d8, 'pmpaddr40'), + (0x3d9, 'pmpaddr41'), + (0x3da, 'pmpaddr42'), + (0x3db, 'pmpaddr43'), + (0x3dc, 'pmpaddr44'), + (0x3dd, 'pmpaddr45'), + (0x3de, 'pmpaddr46'), + (0x3df, 'pmpaddr47'), + (0x3e0, 'pmpaddr48'), + (0x3e1, 'pmpaddr49'), + (0x3e2, 'pmpaddr50'), + (0x3e3, 'pmpaddr51'), + (0x3e4, 'pmpaddr52'), + (0x3e5, 'pmpaddr53'), + (0x3e6, 'pmpaddr54'), + (0x3e7, 'pmpaddr55'), + (0x3e8, 'pmpaddr56'), + (0x3e9, 'pmpaddr57'), + (0x3ea, 'pmpaddr58'), + (0x3eb, 'pmpaddr59'), + (0x3ec, 'pmpaddr60'), + (0x3ed, 'pmpaddr61'), + (0x3ee, 'pmpaddr62'), + (0x3ef, 'pmpaddr63'), + (0x747, 'mseccfg'), + (0x7a0, 'tselect'), + (0x7a1, 'tdata1'), + (0x7a2, 'tdata2'), + (0x7a3, 'tdata3'), + (0x7a4, 'tinfo'), + (0x7a5, 'tcontrol'), + (0x7a8, 'mcontext'), + (0x7aa, 'mscontext'), + (0x7b0, 'dcsr'), + (0x7b1, 'dpc'), + (0x7b2, 'dscratch0'), + (0x7b3, 'dscratch1'), + (0xB00, 'mcycle'), + (0xB02, 'minstret'), + (0xB03, 'mhpmcounter3'), + (0xB04, 'mhpmcounter4'), + (0xB05, 'mhpmcounter5'), + (0xB06, 'mhpmcounter6'), + (0xB07, 'mhpmcounter7'), + (0xB08, 'mhpmcounter8'), + (0xB09, 'mhpmcounter9'), + (0xB0A, 'mhpmcounter10'), + (0xB0B, 'mhpmcounter11'), + (0xB0C, 'mhpmcounter12'), + (0xB0D, 'mhpmcounter13'), + (0xB0E, 'mhpmcounter14'), + (0xB0F, 'mhpmcounter15'), + (0xB10, 'mhpmcounter16'), + (0xB11, 'mhpmcounter17'), + (0xB12, 'mhpmcounter18'), + (0xB13, 'mhpmcounter19'), + (0xB14, 'mhpmcounter20'), + (0xB15, 'mhpmcounter21'), + (0xB16, 'mhpmcounter22'), + (0xB17, 'mhpmcounter23'), + (0xB18, 'mhpmcounter24'), + (0xB19, 'mhpmcounter25'), + (0xB1A, 'mhpmcounter26'), + (0xB1B, 'mhpmcounter27'), + (0xB1C, 'mhpmcounter28'), + (0xB1D, 'mhpmcounter29'), + (0xB1E, 'mhpmcounter30'), + (0xB1F, 'mhpmcounter31'), + (0x323, 'mhpmevent3'), + (0x324, 'mhpmevent4'), + (0x325, 'mhpmevent5'), + (0x326, 'mhpmevent6'), + (0x327, 'mhpmevent7'), + (0x328, 'mhpmevent8'), + (0x329, 'mhpmevent9'), + (0x32A, 'mhpmevent10'), + (0x32B, 'mhpmevent11'), + (0x32C, 'mhpmevent12'), + (0x32D, 'mhpmevent13'), + (0x32E, 'mhpmevent14'), + (0x32F, 'mhpmevent15'), + (0x330, 'mhpmevent16'), + (0x331, 'mhpmevent17'), + (0x332, 'mhpmevent18'), + (0x333, 'mhpmevent19'), + (0x334, 'mhpmevent20'), + (0x335, 'mhpmevent21'), + (0x336, 'mhpmevent22'), + (0x337, 'mhpmevent23'), + (0x338, 'mhpmevent24'), + (0x339, 'mhpmevent25'), + (0x33A, 'mhpmevent26'), + (0x33B, 'mhpmevent27'), + (0x33C, 'mhpmevent28'), + (0x33D, 'mhpmevent29'), + (0x33E, 'mhpmevent30'), + (0x33F, 'mhpmevent31'), + + # Standard Machine RO + (0xF11, 'mvendorid'), + (0xF12, 'marchid'), + (0xF13, 'mimpid'), + (0xF14, 'mhartid'), + (0xF15, 'mconfigptr'), +] + +csrs32 = [ + # Standard Hypervisor R/w + (0x615, 'htimedeltah'), + (0x61A, 'henvcfgh'), + + # Standard User RO + (0xC80, 'cycleh'), + (0xC81, 'timeh'), + (0xC82, 'instreth'), + (0xC83, 'hpmcounter3h'), + (0xC84, 'hpmcounter4h'), + (0xC85, 'hpmcounter5h'), + (0xC86, 'hpmcounter6h'), + (0xC87, 'hpmcounter7h'), + (0xC88, 'hpmcounter8h'), + (0xC89, 'hpmcounter9h'), + (0xC8A, 'hpmcounter10h'), + (0xC8B, 'hpmcounter11h'), + (0xC8C, 'hpmcounter12h'), + (0xC8D, 'hpmcounter13h'), + (0xC8E, 'hpmcounter14h'), + (0xC8F, 'hpmcounter15h'), + (0xC90, 'hpmcounter16h'), + (0xC91, 'hpmcounter17h'), + (0xC92, 'hpmcounter18h'), + (0xC93, 'hpmcounter19h'), + (0xC94, 'hpmcounter20h'), + (0xC95, 'hpmcounter21h'), + (0xC96, 'hpmcounter22h'), + (0xC97, 'hpmcounter23h'), + (0xC98, 'hpmcounter24h'), + (0xC99, 'hpmcounter25h'), + (0xC9A, 'hpmcounter26h'), + (0xC9B, 'hpmcounter27h'), + (0xC9C, 'hpmcounter28h'), + (0xC9D, 'hpmcounter29h'), + (0xC9E, 'hpmcounter30h'), + (0xC9F, 'hpmcounter31h'), + + # Standard Machine RW + (0x310, 'mstatush'), + (0x31A, 'menvcfgh'), + (0x757, 'mseccfgh'), + (0xB80, 'mcycleh'), + (0xB82, 'minstreth'), + (0xB83, 'mhpmcounter3h'), + (0xB84, 'mhpmcounter4h'), + (0xB85, 'mhpmcounter5h'), + (0xB86, 'mhpmcounter6h'), + (0xB87, 'mhpmcounter7h'), + (0xB88, 'mhpmcounter8h'), + (0xB89, 'mhpmcounter9h'), + (0xB8A, 'mhpmcounter10h'), + (0xB8B, 'mhpmcounter11h'), + (0xB8C, 'mhpmcounter12h'), + (0xB8D, 'mhpmcounter13h'), + (0xB8E, 'mhpmcounter14h'), + (0xB8F, 'mhpmcounter15h'), + (0xB90, 'mhpmcounter16h'), + (0xB91, 'mhpmcounter17h'), + (0xB92, 'mhpmcounter18h'), + (0xB93, 'mhpmcounter19h'), + (0xB94, 'mhpmcounter20h'), + (0xB95, 'mhpmcounter21h'), + (0xB96, 'mhpmcounter22h'), + (0xB97, 'mhpmcounter23h'), + (0xB98, 'mhpmcounter24h'), + (0xB99, 'mhpmcounter25h'), + (0xB9A, 'mhpmcounter26h'), + (0xB9B, 'mhpmcounter27h'), + (0xB9C, 'mhpmcounter28h'), + (0xB9D, 'mhpmcounter29h'), + (0xB9E, 'mhpmcounter30h'), + (0xB9F, 'mhpmcounter31h'), +] + +# look up table of position of various arguments that are used by the +# instructions in the encoding files. +arg_lut = {} +arg_lut['rd'] = (11, 7) +arg_lut['rt'] = (19, 15) # source+dest register address. Overlaps rs1. +arg_lut['rs1'] = (19, 15) +arg_lut['rs2'] = (24, 20) +arg_lut['rs3'] = (31, 27) +arg_lut['aqrl'] = (26, 25) +arg_lut['aq'] = (26, 26) +arg_lut['rl'] = (25, 25) +arg_lut['fm'] = (31, 28) +arg_lut['pred'] = (27, 24) +arg_lut['succ'] = (23, 20) +arg_lut['rm'] = (14, 12) +arg_lut['funct3'] = (14, 12) +arg_lut['funct2'] = (26, 25) +arg_lut['imm20'] = (31, 12) +arg_lut['jimm20'] = (31, 12) +arg_lut['imm12'] = (31, 20) +arg_lut['csr'] = (31, 20) +arg_lut['imm12hi'] = (31, 25) +arg_lut['bimm12hi'] = (31, 25) +arg_lut['imm12lo'] = (11, 7) +arg_lut['bimm12lo'] = (11, 7) +arg_lut['zimm'] = (19, 15) +arg_lut['shamt'] = (25, 20) +arg_lut['shamtw'] = (24, 20) +arg_lut['shamtw4'] = (23, 20) +arg_lut['bs'] = (31, 30) # byte select for RV32K AES +arg_lut['rnum'] = (23, 20) # round constant for RV64 AES +arg_lut['rc'] = (29, 25) +arg_lut['imm2'] = (21, 20) +arg_lut['imm3'] = (22, 20) +arg_lut['imm4'] = (23, 20) +arg_lut['imm5'] = (24, 20) +arg_lut['imm6'] = (25, 20) +arg_lut['zimm'] = (19, 15) +arg_lut['opcode'] = (6,0) +arg_lut['funct7'] = (31,25) + +# for vectors +arg_lut['vd'] = (11, 7) +arg_lut['vs3'] = (11, 7) +arg_lut['vs1'] = (19, 15) +arg_lut['vs2'] = (24, 20) +arg_lut['vm'] = (25, 25) +arg_lut['wd'] = (26, 26) +arg_lut['amoop'] = (31, 27) +arg_lut['nf'] = (31, 29) +arg_lut['simm5'] = (19, 15) +arg_lut['zimm10'] = (29, 20) +arg_lut['zimm11'] = (30, 20) + + +#compressed immediates and fields +arg_lut['c_nzuimm10'] = (12,5) +arg_lut['c_uimm7lo'] = (6,5) +arg_lut['c_uimm7hi'] = (12,10) +arg_lut['c_uimm8lo'] = (6,5) +arg_lut['c_uimm8hi'] = (12,10) +arg_lut['c_uimm9lo'] = (6,5) +arg_lut['c_uimm9hi'] = (12,10) +arg_lut['c_nzimm6lo'] = (6,2) +arg_lut['c_nzimm6hi'] = (12,12) +arg_lut['c_imm6lo'] = (6,2) +arg_lut['c_imm6hi'] = (12,12) +arg_lut['c_nzimm10hi'] = (12,12) +arg_lut['c_nzimm10lo'] = (6,2) +arg_lut['c_nzimm18hi'] = (12,12) +arg_lut['c_nzimm18lo'] = (6,2) +arg_lut['c_imm12'] = (12,2) +arg_lut['c_bimm9lo'] = (6,2) +arg_lut['c_bimm9hi'] = (12,10) +arg_lut['c_nzuimm5'] = (6,2) +arg_lut['c_nzuimm6lo'] = (6,2) +arg_lut['c_nzuimm6hi'] = (12, 12) +arg_lut['c_uimm8splo'] = (6,2) +arg_lut['c_uimm8sphi'] = (12, 12) +arg_lut['c_uimm8sp_s'] = (12,7) +arg_lut['c_uimm10splo'] = (6,2) +arg_lut['c_uimm10sphi'] = (12, 12) +arg_lut['c_uimm9splo'] = (6,2) +arg_lut['c_uimm9sphi'] = (12, 12) +arg_lut['c_uimm10sp_s'] = (12,7) +arg_lut['c_uimm9sp_s'] = (12,7) + +arg_lut['rs1_p'] = (9,7) +arg_lut['rs2_p'] = (4,2) +arg_lut['rd_p'] = (4,2) +arg_lut['rd_rs1_n0'] = (11,7) +arg_lut['rd_rs1_p'] = (9,7) +arg_lut['rd_rs1'] = (11,7) +arg_lut['rd_n2'] = (11,7) +arg_lut['rd_n0'] = (11,7) +arg_lut['rs1_n0'] = (11,7) +arg_lut['c_rs2_n0'] = (6,2) +arg_lut['c_rs1_n0'] = (11,7) +arg_lut['c_rs2'] = (6,2) + +# dictionary containing the mapping of the argument to the what the fields in +# the latex table should be +latex_mapping = {} +latex_mapping['imm12'] = 'imm[11:0]' +latex_mapping['rs1'] = 'rs1' +latex_mapping['rs2'] = 'rs2' +latex_mapping['rd'] = 'rd' +latex_mapping['imm20'] = 'imm[31:12]' +latex_mapping['bimm12hi'] = 'imm[12$\\vert$10:5]' +latex_mapping['bimm12lo'] = 'imm[4:1$\\vert$11]' +latex_mapping['imm12hi'] = 'imm[11:5]' +latex_mapping['imm12lo'] = 'imm[4:0]' +latex_mapping['jimm20'] = 'imm[20$\\vert$10:1$\\vert$11$\\vert$19:12]' +latex_mapping['zimm'] = 'uimm' +latex_mapping['shamtw'] = 'shamt' +latex_mapping['rd_p'] = "rd\\,$'$" +latex_mapping['rs1_p'] = "rs1\\,$'$" +latex_mapping['rs2_p'] = "rs2\\,$'$" +latex_mapping['rd_rs1_n0'] = 'rd/rs$\\neq$0' +latex_mapping['rd_rs1_p'] = "rs1\\,$'$/rs2\\,$'$" +latex_mapping['c_rs2'] = 'rs2' +latex_mapping['c_rs2_n0'] = 'rs2$\\neq$0' +latex_mapping['rd_n0'] = 'rd$\\neq$0' +latex_mapping['rs1_n0'] = 'rs1$\\neq$0' +latex_mapping['c_rs1_n0'] = 'rs1$\\neq$0' +latex_mapping['rd_rs1'] = 'rd/rs1' +latex_mapping['c_nzuimm10'] = "nzuimm[5:4$\\vert$9:6$\\vert$2$\\vert$3]" +latex_mapping['c_uimm7lo'] = 'uimm[2$\\vert$6]' +latex_mapping['c_uimm7hi'] = 'uimm[5:3]' +latex_mapping['c_uimm8lo'] = 'uimm[7:6]' +latex_mapping['c_uimm8hi'] = 'uimm[5:3]' +latex_mapping['c_uimm9lo'] = 'uimm[7:6]' +latex_mapping['c_uimm9hi'] = 'uimm[5:4$\\vert$8]' +latex_mapping['c_nzimm6lo'] = 'nzimm[4:0]' +latex_mapping['c_nzimm6hi'] = 'nzimm[5]' +latex_mapping['c_imm6lo'] = 'imm[4:0]' +latex_mapping['c_imm6hi'] = 'imm[5]' +latex_mapping['c_nzimm10hi'] = 'nzimm[9]' +latex_mapping['c_nzimm10lo'] = 'nzimm[4$\\vert$6$\\vert$8:7$\\vert$5]' +latex_mapping['c_nzimm18hi'] = 'nzimm[17]' +latex_mapping['c_nzimm18lo'] = 'nzimm[16:12]' +latex_mapping['c_imm12'] = 'imm[11$\\vert$4$\\vert$9:8$\\vert$10$\\vert$6$\\vert$7$\\vert$3:1$\\vert$5]' +latex_mapping['c_bimm9lo'] = 'imm[7:6$\\vert$2:1$\\vert$5]' +latex_mapping['c_bimm9hi'] = 'imm[8$\\vert$4:3]' +latex_mapping['c_nzuimm5'] = 'nzuimm[4:0]' +latex_mapping['c_nzuimm6lo'] = 'nzuimm[4:0]' +latex_mapping['c_nzuimm6hi'] = 'nzuimm[5]' +latex_mapping['c_uimm8splo'] = 'uimm[4:2$\\vert$7:6]' +latex_mapping['c_uimm8sphi'] = 'uimm[5]' +latex_mapping['c_uimm8sp_s'] = 'uimm[5:2$\\vert$7:6]' +latex_mapping['c_uimm10splo'] = 'uimm[4$\\vert$9:6]' +latex_mapping['c_uimm10sphi'] = 'uimm[5]' +latex_mapping['c_uimm9splo'] = 'uimm[4:3$\\vert$8:6]' +latex_mapping['c_uimm9sphi'] = 'uimm[5]' +latex_mapping['c_uimm10sp_s'] = 'uimm[5:4$\\vert$9:6]' +latex_mapping['c_uimm9sp_s'] = 'uimm[5:3$\\vert$8:6]' + +# created a dummy instruction-dictionary like dictionary for all the instruction +# types so that the same logic can be used to create their tables +latex_inst_type = {} +latex_inst_type['R-type'] = {} +latex_inst_type['R-type']['variable_fields'] = ['opcode', 'rd', 'funct3', \ + 'rs1', 'rs2', 'funct7'] +latex_inst_type['R4-type'] = {} +latex_inst_type['R4-type']['variable_fields'] = ['opcode', 'rd', 'funct3', \ + 'rs1', 'rs2', 'funct2', 'rs3'] +latex_inst_type['I-type'] = {} +latex_inst_type['I-type']['variable_fields'] = ['opcode', 'rd', 'funct3', \ + 'rs1', 'imm12'] +latex_inst_type['S-type'] = {} +latex_inst_type['S-type']['variable_fields'] = ['opcode', 'imm12lo', 'funct3', \ + 'rs1', 'rs2', 'imm12hi'] +latex_inst_type['B-type'] = {} +latex_inst_type['B-type']['variable_fields'] = ['opcode', 'bimm12lo', 'funct3', \ + 'rs1', 'rs2', 'bimm12hi'] +latex_inst_type['U-type'] = {} +latex_inst_type['U-type']['variable_fields'] = ['opcode', 'rd', 'imm20'] +latex_inst_type['J-type'] = {} +latex_inst_type['J-type']['variable_fields'] = ['opcode', 'rd', 'jimm20'] +latex_fixed_fields = [] +latex_fixed_fields.append((31,25)) +latex_fixed_fields.append((24,20)) +latex_fixed_fields.append((19,15)) +latex_fixed_fields.append((14,12)) +latex_fixed_fields.append((11,7)) +latex_fixed_fields.append((6,0)) diff --git a/parse.py b/parse.py new file mode 100755 index 0000000..970c29d --- /dev/null +++ b/parse.py @@ -0,0 +1,872 @@ +#!/usr/bin/env python3 + +from constants import * +import re +import glob +import os +import pprint +import logging +import collections +import yaml +import sys + +pp = pprint.PrettyPrinter(indent=2) +logging.basicConfig(level=logging.INFO, format='%(levelname)s:: %(message)s') + +def process_enc_line(line, ext): + ''' + This function processes each line of the encoding files (rv*). As part of + the processing, the function ensures that the encoding is legal through the + following checks:: + + - there is no over specification (same bits assigned different values) + - there is no under specification (some bits not assigned values) + - bit ranges are in the format hi..lo=val where hi > lo + - value assigned is representable in the bit range + - also checks that the mapping of arguments of an instruction exists in + arg_lut. + + If the above checks pass, then the function returns a tuple of the name and + a dictionary containing basic information of the instruction which includes: + - variables: list of arguments used by the instruction whose mapping + exists in the arg_lut dictionary + - encoding: this contains the 32-bit encoding of the instruction where + '-' is used to represent position of arguments and 1/0 is used to + reprsent the static encoding of the bits + - extension: this field contains the rv* filename from which this + instruction was included + - match: hex value representing the bits that need to match to detect + this instruction + - mask: hex value representin the bits that need to be masked to extract + the value required for matching. + ''' + single_dict = {} + + # fill all bits with don't care. we use '-' to represent don't care + # TODO: hardcoded for 32-bits. + encoding = ['-'] * 32 + + # get the name of instruction by splitting based on the first space + [name, remaining] = line.split(' ', 1) + + # replace dots with underscores as dot doesn't work with C/Sverilog, etc + name = name.replace('.', '_') + + # remove leading whitespaces + remaining = remaining.lstrip() + + # check each field for it's length and overlapping bits + # ex: 1..0=5 will result in an error --> x overlapping bits + temp_instr = ['-'] * 32 + entries = [ + x[0] for x in re.findall( + r'((\d)+\.\.(\d)+\=((0b\d+)|(0x\d+)|(\d)+))*', + remaining) if x[0] != '' + ] + for temp_entry in entries: + entry = temp_entry.split('=')[0] + f1, f2 = entry.split('..') + for ind in range(int(f1), int(f2)): + + # overlapping bits + if temp_instr[ind] == 'X': + logging.error( + f'{line.split(" ")[0]:<10} has {ind} bit overlapping in it\'s opcodes' + ) + raise SystemExit(1) + temp_instr[ind] = 'X' + + # check x < y + if int(f1) < int(f2): + logging.error( + f'{line.split(" ")[0]:<10} has position {f1} less than position {f2} in it\'s encoding' + ) + raise SystemExit(1) + + # illegal value assigned as per bit width + entry_value = temp_entry.split('=')[1] + temp_base = 16 if 'x' in entry_value else 2 if 'b' in entry_value else 10 + if len(str(int(entry_value, + temp_base))[2:]) > (int(f1) - int(f2)): + logging.error( + f'{line.split(" ")[0]:<10} has an illegal value {entry_value} assigned as per the bit width {f1 - f2}' + ) + raise SystemExit(1) + + # extract bit pattern assignments of the form hi..lo=val. fixed_ranges is a + # regex expression present in constants.py. The extracted patterns are + # captured as a list in args where each entry is a tuple (msb, lsb, value) + args = fixed_ranges.sub(' ', remaining) + + # parse through the args and assign constants 1/0 to bits which need to be + # hardcoded for this instruction + for (msb, lsb, value) in fixed_ranges.findall(remaining): + value = int(value, 0) + msb = int(msb, 0) + lsb = int(lsb, 0) + value = f"{value:032b}" + for i in range(0, msb - lsb + 1): + encoding[31 - (i + lsb)] = value[31 - i] + + # do the same as above but for = pattern. single_fixed is a regex + # expression present in constants.py + for (lsb, value, drop) in single_fixed.findall(remaining): + lsb = int(lsb, 0) + value = int(value, 0) + encoding[31 - lsb] = str(value) + + # convert the list of encodings into a single string for match and mask + match = "".join(encoding).replace('-','0') + mask = "".join(encoding).replace('0','1').replace('-','0') + + # check if all args of the instruction are present in arg_lut present in + # constants.py + args = single_fixed.sub(' ', args).split() + for a in args: + if a not in arg_lut: + logging.error(f' Found variable {a} in instruction {name} whose mapping in arg_lut does not exist') + raise SystemExit(1) + + # update the fields of the instruction as a dict and return back along with + # the name of the instruction + single_dict['encoding'] = "".join(encoding) + single_dict['variable_fields'] = args + single_dict['extension'] = [ext.split('/')[-1]] + single_dict['match']=hex(int(match,2)) + single_dict['mask']=hex(int(mask,2)) + + return (name, single_dict) + + +def create_inst_dict(file_filter, include_pseudo=False): + ''' + This function return a dictionary containing all instructions associated + with an extension defined by the file_filter input. The file_filter input + needs to be rv* file name with out the 'rv' prefix i.e. '_i', '32_i', etc. + + Each node of the dictionary will correspond to an instruction which again is + a dictionary. The dictionary contents of each instruction includes: + - variables: list of arguments used by the instruction whose mapping + exists in the arg_lut dictionary + - encoding: this contains the 32-bit encoding of the instruction where + '-' is used to represent position of arguments and 1/0 is used to + reprsent the static encoding of the bits + - extension: this field contains the rv* filename from which this + instruction was included + - match: hex value representing the bits that need to match to detect + this instruction + - mask: hex value representin the bits that need to be masked to extract + the value required for matching. + + In order to build this dictionary, the function does 2 passes over the same + rv file. The first pass is to extract all standard + instructions. In this pass, all pseudo ops and imported instructions are + skipped. For each selected line of the file, we call process_enc_line + function to create the above mentioned dictionary contents of the + instruction. Checks are performed in this function to ensure that the same + instruction is not added twice to the overall dictionary. + + In the second pass, this function parses only pseudo_ops. For each pseudo_op + this function checks if the dependent extension and instruction, both, exit + before parsing it. The pseudo op is only added to the overall dictionary is + the dependent instruction is not present in the dictionary, else its + skipped. + + + ''' + opcodes_dir = f'./' + instr_dict = {} + + # file_names contains all files to be parsed in the riscv-opcodes directory + file_names = [] + for fil in file_filter: + file_names += glob.glob(f'{opcodes_dir}{fil}') + + # first pass if for standard/regular instructions + logging.debug('Collecting standard instructions first') + for f in file_names: + logging.debug(f'Parsing File: {f}') + with open(f) as fp: + lines = (line.rstrip() + for line in fp) # All lines including the blank ones + lines = list(line for line in lines if line) # Non-blank lines + lines = list( + line for line in lines + if not line.startswith("#")) # remove comment lines + + # go through each line of the file + for line in lines: + # if the an instruction needs to be imported then go to the + # respective file and pick the line that has the instruction. + # The variable 'line' will now point to the new line from the + # imported file + + # ignore all lines starting with $import and $pseudo + if '$import' in line or '$pseudo' in line: + continue + logging.debug(f' Processing line: {line}') + + # call process_enc_line to get the data about the current + # instruction + (name, single_dict) = process_enc_line(line, f) + + # if an instruction has already been added to the filtered + # instruction dictionary throw an error saying the given + # instruction is already imported and raise SystemExit + if name in instr_dict: + var = instr_dict[name]["extension"] + if instr_dict[name]['encoding'] != single_dict['encoding']: + err_msg = f'instruction : {name} from ' + err_msg += f'{f.split("/")[-1]} is already ' + err_msg += f'added from {var} but each have different encodings for the same instruction' + logging.error(err_msg) + raise SystemExit(1) + instr_dict[name]['extension'].append(single_dict['extension']) + + # update the final dict with the instruction + instr_dict[name] = single_dict + + # second pass if for pseudo instructions + logging.debug('Collecting pseudo instructions now') + for f in file_names: + logging.debug(f'Parsing File: {f}') + with open(f) as fp: + lines = (line.rstrip() + for line in fp) # All lines including the blank ones + lines = list(line for line in lines if line) # Non-blank lines + lines = list( + line for line in lines + if not line.startswith("#")) # remove comment lines + + # go through each line of the file + for line in lines: + + # ignore all lines not starting with $pseudo + if '$pseudo' not in line: + continue + logging.debug(f' Processing line: {line}') + + # use the regex pseudo_regex from constants.py to find the dependent + # extension, dependent instruction, the pseudo_op in question and + # its encoding + (ext, orig_inst, pseudo_inst, line) = pseudo_regex.findall(line)[0] + + # check if the file of the dependent extension exist. Throw error if + # it doesn't + if not os.path.exists(ext): + ext1 = f'unratified/{ext}' + if not os.path.exists(ext1): + logging.error(f'Pseudo op {pseudo_inst} in {f} depends on {ext} which is not available') + raise SystemExit(1) + else: + ext = ext1 + + # check if the dependent instruction exist in the dependent + # extension. Else throw error. + found = False + for oline in open(ext): + if not re.findall(f'^\s*{orig_inst}',oline): + continue + else: + found = True + break + if not found: + logging.error(f'Orig instruction {orig_inst} not found in {ext}. Required by pseudo_op {pseudo_inst} present in {f}') + raise SystemExit(1) + + + # add the pseudo_op to the dictionary only if the original + # instruction is not already in the dictionary. + if orig_inst.replace('.','_') not in instr_dict or include_pseudo: + (name, single_dict) = process_enc_line(pseudo_inst + ' ' + line, f) + + # update the final dict with the instruction + if name not in instr_dict: + instr_dict[name] = single_dict + else: + logging.debug(f'Skipping pseudo_op {pseudo_inst} since original instruction {orig_inst} already selected in list') + + # third pass if for imported instructions + logging.debug('Collecting imported instructions') + for f in file_names: + logging.debug(f'Parsing File: {f}') + with open(f) as fp: + lines = (line.rstrip() + for line in fp) # All lines including the blank ones + lines = list(line for line in lines if line) # Non-blank lines + lines = list( + line for line in lines + if not line.startswith("#")) # remove comment lines + + # go through each line of the file + for line in lines: + # if the an instruction needs to be imported then go to the + # respective file and pick the line that has the instruction. + # The variable 'line' will now point to the new line from the + # imported file + + # ignore all lines starting with $import and $pseudo + if '$import' not in line : + continue + logging.debug(f' Processing line: {line}') + + (import_ext, reg_instr) = imported_regex.findall(line)[0] + + # check if the file of the dependent extension exist. Throw error if + # it doesn't + if not os.path.exists(import_ext): + ext1 = f'unratified/{import_ext}' + if not os.path.exists(ext1): + logging.error(f'Instruction {reg_instr} in {f} cannot be imported from {import_ext}') + raise SystemExit(1) + else: + ext = ext1 + else: + ext = import_ext + + # check if the dependent instruction exist in the dependent + # extension. Else throw error. + found = False + for oline in open(ext): + if not re.findall(f'^\s*{reg_instr}',oline): + continue + else: + found = True + break + if not found: + logging.error(f'imported instruction {reg_instr} not found in {ext}. Required by {line} present in {f}') + logging.error(f'Note: you cannot import pseudo ops.') + raise SystemExit(1) + + # call process_enc_line to get the data about the current + # instruction + (name, single_dict) = process_enc_line(oline, f) + + # if an instruction has already been added to the filtered + # instruction dictionary throw an error saying the given + # instruction is already imported and raise SystemExit + if name in instr_dict: + var = instr_dict[name]["extension"] + if instr_dict[name]['encoding'] != single_dict['encoding']: + err_msg = f'imported instruction : {name} in ' + err_msg += f'{f.split("/")[-1]} is already ' + err_msg += f'added from {var} but each have different encodings for the same instruction' + logging.error(err_msg) + raise SystemExit(1) + instr_dict[name]['extension'].append(single_dict['extension']) + + # update the final dict with the instruction + instr_dict[name] = single_dict + return instr_dict + +def make_priv_latex_table(): + latex_file = open('priv-instr-table.tex','w') + type_list = ['R-type','I-type'] + system_instr = ['_h','_s','_system','_svinval', '64_h'] + dataset_list = [ (system_instr, 'Trap-Return Instructions',['sret','mret'], False) ] + dataset_list.append((system_instr, 'Interrupt-Management Instructions',['wfi'], False)) + dataset_list.append((system_instr, 'Supervisor Memory-Management Instructions',['sfence_vma'], False)) + dataset_list.append((system_instr, 'Hypervisor Memory-Management Instructions',['hfence_vvma', 'hfence_gvma'], False)) + dataset_list.append((system_instr, 'Hypervisor Virtual-Machine Load and Store Instructions', + ['hlv_b','hlv_bu', 'hlv_h','hlv_hu', 'hlv_w', 'hlvx_hu', 'hlvx_wu', 'hsv_b', 'hsv_h','hsv_w'], False)) + dataset_list.append((system_instr, 'Hypervisor Virtual-Machine Load and Store Instructions, RV64 only', ['hlv_wu','hlv_d','hsv_d'], False)) + dataset_list.append((system_instr, 'Svinval Memory-Management Instructions', ['sinval_vma', 'sfence_w_inval','sfence_inval_ir', 'hinval_vvma','hinval_gvma'], False)) + caption = '\\caption{RISC-V Privileged Instructions}' + make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) + + latex_file.close() + +def make_latex_table(): + ''' + This function is mean to create the instr-table.tex that is meant to be used + by the riscv-isa-manual. This function basically creates a single latext + file of multiple tables with each table limited to a single page. Only the + last table is assigned a latex-caption. + + For each table we assign a type-list which capture the different instruction + types (R, I, B, etc) that will be required for the table. Then we select the + list of extensions ('_i, '32_i', etc) whose instructions are required to + populate the table. For each extension or collection of extension we can + assign Title, such that in the end they appear as subheadings within + the table (note these are inlined headings and not captions of the table). + + All of the above information is collected/created and sent to + make_ext_latex_table function to dump out the latex contents into a file. + + The last table only has to be given a caption - as per the policy of the + riscv-isa-manual. + ''' + # open the file and use it as a pointer for all further dumps + latex_file = open('instr-table.tex','w') + + # create the rv32i table first. Here we set the caption to empty. We use the + # files rv_i and rv32_i to capture instructions relevant for rv32i + # configuration. The dataset is a list of 4-element tuples : + # (list_of_extensions, title, list_of_instructions, include_pseudo_ops). If list_of_instructions + # is empty then it indicates that all instructions of the all the extensions + # in list_of_extensions need to be dumped. If not empty, then only the + # instructions listed in list_of_instructions will be dumped into latex. + caption = '' + type_list = ['R-type','I-type','S-type','B-type','U-type','J-type'] + dataset_list = [(['_i','32_i'], 'RV32I Base Instruction Set', [], True)] + make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) + + type_list = ['R-type','I-type','S-type'] + dataset_list = [(['64_i'], 'RV64I Base Instruction Set (in addition to RV32I)', [], False)] + dataset_list.append((['_zifencei'], 'RV32/RV64 Zifencei Standard Extension', [], False)) + dataset_list.append((['_zicsr'], 'RV32/RV64 Zicsr Standard Extension', [], False)) + dataset_list.append((['_m','32_m'], 'RV32M Standard Extension', [], False)) + dataset_list.append((['64_m'],'RV64M Standard Extension (in addition to RV32M)', [], False)) + make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) + + type_list = ['R-type'] + dataset_list = [(['_a'],'RV32A Standard Extension', [], False)] + dataset_list.append((['64_a'],'RV64A Standard Extension (in addition to RV32A)', [], False)) + make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) + + type_list = ['R-type','R4-type','I-type','S-type'] + dataset_list = [(['_f'],'RV32F Standard Extension', [], False)] + dataset_list.append((['64_f'],'RV64F Standard Extension (in addition to RV32F)', [], False)) + make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) + + type_list = ['R-type','R4-type','I-type','S-type'] + dataset_list = [(['_d'],'RV32D Standard Extension', [], False)] + dataset_list.append((['64_d'],'RV64D Standard Extension (in addition to RV32D)', [], False)) + make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) + + type_list = ['R-type','R4-type','I-type','S-type'] + dataset_list = [(['_q'],'RV32Q Standard Extension', [], False)] + dataset_list.append((['64_q'],'RV64Q Standard Extension (in addition to RV32Q)', [], False)) + make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) + + caption = '\\caption{Instruction listing for RISC-V}' + type_list = ['R-type','R4-type','I-type','S-type'] + dataset_list = [(['_zfh', '_d_zfh','_q_zfh'],'RV32Zfh Standard Extension', [], False)] + dataset_list.append((['64_zfh'],'RV64Zfh Standard Extension (in addition to RV32Zfh)', [], False)) + make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) + + ## The following is demo to show that Compressed instructions can also be + # dumped in the same manner as above + + #type_list = [''] + #dataset_list = [(['_c', '32_c', '32_c_f','_c_d'],'RV32C Standard Extension', [])] + #dataset_list.append((['64_c'],'RV64C Standard Extension (in addition to RV32C)', [])) + #make_ext_latex_table(type_list, dataset_list, latex_file, 16, caption) + + latex_file.close() + +def make_ext_latex_table(type_list, dataset, latex_file, ilen, caption): + ''' + For a given collection of extensions this function dumps out a complete + latex table which includes the encodings of the instructions. + + The ilen input indicates the length of the instruction for which the table + is created. + + The caption input is used to create the latex-table caption. + + The type_list input is a list of instruction types (R, I, B, etc) that are + treated as header for each table. Each table will have its own requirements + and type_list must include all the instruction-types that the table needs. + Note, all elements of this list must be present in the latex_inst_type + dictionary defined in constants.py + + The latex_file is a file pointer to which the latex-table will dumped into + + The dataset is a list of 3-element tuples containing: + (list_of_extensions, title, list_of_instructions) + The list_of_extensions must contain all the set of extensions whose + instructions must be populated under a given title. If list_of_instructions + is not empty, then only those instructions mentioned in list_of_instructions + present in the extension will be dumped into the latex-table, other + instructions will be ignored. + + Once the above inputs are received then function first creates table entries + for the instruction types. To simplify things, we maintain a dictionary + called latex_inst_type in constants.py which is created in the same way the + instruction dictionary is created. This allows us to re-use the same logic + to create the instruction types table as well + + Once the header is created, we then parse through every entry in the + dataset. For each list dataset entry we use the create_inst_dict function to + create an exhaustive list of instructions associated with the respective + collection of the extension of that dataset. Then we apply the instruction + filter, if any, indicated by the list_of_instructions of that dataset. + Thereon, for each instruction we create a latex table entry. + + Latex table specification for ilen sized instructions: + Each table is created with ilen+1 columns - ilen columns for each bit of the + instruction and one column to hold the name of the instruction. + + For each argument of an instruction we use the arg_lut from constants.py + to identify its position in the encoding, and thus create a multicolumn + entry with the name of the argument as the data. For hardcoded bits, we + do the same where we capture a string of continuous 1s and 0s, identify + the position and assign the same string as the data of the + multicolumn entry in the table. + + ''' + column_size = "".join(['p{0.002in}']*(ilen+1)) + + type_entries = ''' + \\multicolumn{3}{l}{31} & + \\multicolumn{2}{r}{27} & + \\multicolumn{1}{c}{26} & + \\multicolumn{1}{r}{25} & + \\multicolumn{3}{l}{24} & + \\multicolumn{2}{r}{20} & + \\multicolumn{3}{l}{19} & + \\multicolumn{2}{r}{15} & + \\multicolumn{2}{l}{14} & + \\multicolumn{1}{r}{12} & + \\multicolumn{4}{l}{11} & + \\multicolumn{1}{r}{7} & + \\multicolumn{6}{l}{6} & + \\multicolumn{1}{r}{0} \\\\ + \\cline{2-33}\n& \n\n +''' if ilen == 32 else ''' + \\multicolumn{1}{c}{15} & + \\multicolumn{1}{c}{14} & + \\multicolumn{1}{c}{13} & + \\multicolumn{1}{c}{12} & + \\multicolumn{1}{c}{11} & + \\multicolumn{1}{c}{10} & + \\multicolumn{1}{c}{9} & + \\multicolumn{1}{c}{8} & + \\multicolumn{1}{c}{7} & + \\multicolumn{1}{c}{6} & + \\multicolumn{1}{c}{5} & + \\multicolumn{1}{c}{4} & + \\multicolumn{1}{c}{3} & + \\multicolumn{1}{c}{2} & + \\multicolumn{1}{c}{1} & + \\multicolumn{1}{c}{0} \\\\ + \\cline{2-17}\n& \n\n +''' + + # depending on the type_list input we create a subset dictionary of + # latex_inst_type dictionary present in constants.py + type_dict = {key: value for key, value in latex_inst_type.items() if key in type_list} + + # iterate ovr each instruction type and create a table entry + for t in type_dict: + fields = [] + + # first capture all "arguments" of the type (funct3, funct7, rd, etc) + # and capture their positions using arg_lut. + for f in type_dict[t]['variable_fields']: + (msb, lsb) = arg_lut[f] + name = f if f not in latex_mapping else latex_mapping[f] + fields.append((msb, lsb, name)) + + # iterate through the 32 bits, starting from the msb, and assign + # argument names to the relevant portions of the instructions. This + # information is stored as a 3-element tuple containing the msb, lsb + # position of the arugment and the name of the argument. + msb = ilen - 1 + y = '' + for r in range(0,ilen): + if y != '': + fields.append((msb,ilen-1-r+1,y)) + y = '' + msb = ilen-1-r-1 + if r == 31: + if y != '': + fields.append((msb, 0, y)) + y = '' + + # sort the arguments in decreasing order of msb position + fields.sort(key=lambda y: y[0], reverse=True) + + # for each argument/string of 1s or 0s, create a multicolumn latex table + # entry + entry = '' + for r in range(len(fields)): + (msb, lsb, name) = fields[r] + if r == len(fields)-1: + entry += f'\\multicolumn{{ {msb -lsb +1} }}{{|c|}}{{ {name} }} & {t} \\\\ \n' + elif r == 0: + entry += f'\\multicolumn{{ {msb- lsb + 1} }}{{|c|}}{{ {name} }} &\n' + else: + entry += f'\\multicolumn{{ {msb -lsb + 1} }}{{c|}}{{ {name} }} &\n' + entry += f'\\cline{{2-{ilen+1}}}\n&\n\n' + type_entries += entry + + # for each entry in the dataset create a table + content = '' + for (ext_list, title, filter_list, include_pseudo) in dataset: + instr_dict = {} + + # for all extensions list in ext_list, create a dictionary of + # instructions associated with those extensions. + for e in ext_list: + instr_dict.update(create_inst_dict(['rv'+e], include_pseudo)) + + # if filter_list is not empty then use that as the official set of + # instructions that need to be dumped into the latex table + inst_list = list(instr_dict.keys()) if not filter_list else filter_list + + # for each instruction create an latex table entry just like how we did + # above with the instruction-type table. + instr_entries = '' + for inst in inst_list: + if inst not in instr_dict: + logging.error(f'in make_ext_latex_table: Instruction: {inst} not found in instr_dict') + raise SystemExit(1) + fields = [] + + # only if the argument is available in arg_lut we consume it, else + # throw error. + for f in instr_dict[inst]['variable_fields']: + if f not in arg_lut: + logging.error(f'Found variable {f} in instruction {inst} whose mapping is not available') + raise SystemExit(1) + (msb,lsb) = arg_lut[f] + name = f.replace('_','.') if f not in latex_mapping else latex_mapping[f] + fields.append((msb, lsb, name)) + + msb = ilen -1 + y = '' + if ilen == 16: + encoding = instr_dict[inst]['encoding'][16:] + else: + encoding = instr_dict[inst]['encoding'] + for r in range(0,ilen): + x = encoding [r] + if ((msb, ilen-1-r+1)) in latex_fixed_fields: + fields.append((msb,ilen-1-r+1,y)) + msb = ilen-1-r + y = '' + if x == '-': + if y != '': + fields.append((msb,ilen-1-r+1,y)) + y = '' + msb = ilen-1-r-1 + else: + y += str(x) + if r == ilen-1: + if y != '': + fields.append((msb, 0, y)) + y = '' + + fields.sort(key=lambda y: y[0], reverse=True) + entry = '' + for r in range(len(fields)): + (msb, lsb, name) = fields[r] + if r == len(fields)-1: + entry += f'\\multicolumn{{ {msb -lsb +1} }}{{|c|}}{{ {name} }} & {inst.upper().replace("_",".")} \\\\ \n' + elif r == 0: + entry += f'\\multicolumn{{ {msb- lsb + 1} }}{{|c|}}{{ {name} }} &\n' + else: + entry += f'\\multicolumn{{ {msb -lsb + 1} }}{{c|}}{{ {name} }} &\n' + entry += f'\\cline{{2-{ilen+1}}}\n&\n\n' + instr_entries += entry + + # once an entry of the dataset is completed we create the whole table + # with the title of that dataset as sub-heading (sort-of) + if title != '': + content += f''' + +\\multicolumn{{{ilen}}}{{c}}{{}} & \\\\ +\\multicolumn{{{ilen}}}{{c}}{{\\bf {title} }} & \\\\ +\\cline{{2-{ilen+1}}} + + & +{instr_entries} +''' + else: + content += f''' +{instr_entries} +''' + + + header = f''' +\\newpage + +\\begin{{table}}[p] +\\begin{{small}} +\\begin{{center}} + \\begin{{tabular}} {{{column_size}l}} + {" ".join(['&']*ilen)} \\\\ + + & +{type_entries} +''' + endtable=f''' + +\\end{{tabular}} +\\end{{center}} +\\end{{small}} +{caption} +\\end{{table}} +''' + # dump the contents and return + latex_file.write(header+content+endtable) + + +def make_chisel(instr_dict): + + chisel_names='' + cause_names_str='' + csr_names_str = '' + for i in instr_dict: + chisel_names += f' def {i.upper().replace(".","_"):<18s} = BitPat("b{instr_dict[i]["encoding"].replace("-","?")}")\n' + for num, name in causes: + cause_names_str += f' val {name.lower().replace(" ","_")} = {hex(num)}\n' + cause_names_str += ''' val all = { + val res = collection.mutable.ArrayBuffer[Int]() +''' + for num, name in causes: + cause_names_str += f' res += {name.lower().replace(" ","_")}\n' + cause_names_str += ''' res.toArray + }''' + + for num, name in csrs+csrs32: + csr_names_str += f' val {name} = {hex(num)}\n' + csr_names_str += ''' val all = { + val res = collection.mutable.ArrayBuffer[Int]() +''' + for num, name in csrs: + csr_names_str += f''' res += {name}\n''' + csr_names_str += ''' res.toArray + } + val all32 = { + val res = collection.mutable.ArrayBuffer(all:_*) +''' + for num, name in csrs32: + csr_names_str += f''' res += {name}\n''' + csr_names_str += ''' res.toArray + }''' + + chisel_file = open('inst.chisel','w') + chisel_file.write(f''' +/* Automatically generated by parse_opcodes */ +object Instructions {{ +{chisel_names} +}} +object Causes {{ +{cause_names_str} +}} +object CSRs {{ +{csr_names_str} +}} +''') + chisel_file.close() + +def make_rust(instr_dict): + mask_match_str= '' + for i in instr_dict: + mask_match_str += f'const MATCH_{i.upper().replace(".","_")}: u32 = {(instr_dict[i]["match"])};\n' + mask_match_str += f'const MASK_{i.upper().replace(".","_")}: u32 = {(instr_dict[i]["mask"])};\n' + for num, name in csrs+csrs32: + mask_match_str += f'const CSR_{name.upper()}: u16 = {hex(num)};\n' + for num, name in causes: + mask_match_str += f'const CAUSE_{name.upper().replace(" ","_")}: u8 = {hex(num)};\n' + rust_file = open('inst.rs','w') + rust_file.write(f''' +/* Automatically generated by parse_opcodes */ +{mask_match_str} +''') + rust_file.close() + +def make_sverilog(instr_dict): + names_str = '' + for i in instr_dict: + names_str += f" localparam [31:0] {i.upper().replace('.','_'):<18s} = 32'b{instr_dict[i]['encoding'].replace('-','?')};\n" + names_str += ' /* CSR Addresses */\n' + for num, name in csrs+csrs32: + names_str += f" localparam logic [11:0] CSR_{name.upper()} = 12'h{hex(num)[2:]};\n" + + sverilog_file = open('inst.sverilog','w') + sverilog_file.write(f''' +/* Automatically generated by parse_opcodes */ +package riscv_instr; +{names_str} +endpackage +''') + sverilog_file.close() +def make_c(instr_dict): + mask_match_str = '' + declare_insn_str = '' + for i in instr_dict: + mask_match_str += f'#define MATCH_{i.upper().replace(".","_")} {instr_dict[i]["match"]}\n' + mask_match_str += f'#define MASK_{i.upper().replace(".","_")} {instr_dict[i]["mask"]}\n' + declare_insn_str += f'DECLARE_INSN({i.replace(".","_")}, MATCH_{i.upper().replace(".","_")}, MASK_{i.upper().replace(".","_")})\n' + + csr_names_str = '' + declare_csr_str = '' + for num, name in csrs+csrs32: + csr_names_str += f'#define CSR_{name.upper()} {hex(num)}\n' + declare_csr_str += f'DECLARE_CSR({name}, CSR_{name.upper()})\n' + + causes_str= '' + declare_cause_str = '' + for num, name in causes: + causes_str += f"#define CAUSE_{name.upper().replace(' ', '_')} {hex(num)}\n" + declare_cause_str += f"DECLARE_CAUSE(\"{name}\", CAUSE_{name.upper().replace(' ','_')})\n" + + with open('encoding.h', 'r') as file: + enc_header = file.read() + + commit = os.popen('git log -1 --format="format:%h"').read() + enc_file = open('encoding.out.h','w') + enc_file.write(f''' +/* +* This file is auto-generated by running 'make' in +* https://github.com/riscv/riscv-opcodes ({commit}) +*/ +{enc_header} +/* Automatically generated by parse_opcodes. */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +{mask_match_str} +{csr_names_str} +{causes_str} +#endif +#ifdef DECLARE_INSN +{declare_insn_str} +#endif +#ifdef DECLARE_CSR +{declare_csr_str} +#endif +#ifdef DECLARE_CAUSE +{declare_cause_str} +#endif +''') + enc_file.close() + +if __name__ == "__main__": + print(f'Running with args : {sys.argv}') + + extensions = sys.argv[1:] + for i in ['-c','-latex','-chisel','-sverilog','-rust']: + if i in extensions: + extensions.remove(i) + print(f'Extensions selected : {extensions}') + instr_dict = create_inst_dict(extensions) + with open('instr_dict.yaml', 'w') as outfile: + yaml.dump(instr_dict, outfile, default_flow_style=False) + instr_dict = collections.OrderedDict(sorted(instr_dict.items())) + + if '-c' in sys.argv[1:]: + make_c(instr_dict) + logging.info('encoding.out.h generated successfully') + + if '-chisel' in sys.argv[1:]: + make_chisel(instr_dict) + logging.info('inst.chisel generated successfully') + + if '-sverilog' in sys.argv[1:]: + make_sverilog(instr_dict) + logging.info('inst.sverilog generated successfully') + + if '-rust' in sys.argv[1:]: + make_rust(instr_dict) + logging.info('inst.rs generated successfully') + + if '-latex' in sys.argv[1:]: + make_latex_table() + logging.info('instr-table.tex generated successfully') + make_priv_latex_table() + logging.info('priv-instr-table.tex generated successfully') diff --git a/parse_opcodes b/parse_opcodes deleted file mode 100755 index a9445bc..0000000 --- a/parse_opcodes +++ /dev/null @@ -1,1240 +0,0 @@ -#!/usr/bin/env python3 - -import math -import sys -import tokenize -from collections import OrderedDict - -namelist = [] -match = OrderedDict() -mask = OrderedDict() -pseudos = {} -arguments = {} - -arglut = {} -arglut['rd'] = (11,7) -arglut['rt'] = (19,15) # source+dest register address. Overlaps rs1. -arglut['rs1'] = (19,15) -arglut['rs2'] = (24,20) -arglut['rs3'] = (31,27) -arglut['aqrl'] = (26,25) -arglut['fm'] = (31,28) -arglut['pred'] = (27,24) -arglut['succ'] = (23,20) -arglut['rm'] = (14,12) -arglut['funct3'] = (14,12) -arglut['imm20'] = (31,12) -arglut['jimm20'] = (31,12) -arglut['imm12'] = (31,20) -arglut['imm12hi'] = (31,25) -arglut['bimm12hi'] = (31,25) -arglut['imm12lo'] = (11,7) -arglut['bimm12lo'] = (11,7) -arglut['zimm'] = (19,15) -arglut['shamt'] = (25,20) -arglut['shamtw'] = (24,20) -arglut['bs'] = (31,30) # byte select for RV32K AES -arglut['rnum'] = (23,20) # round constant for RV64 AES -arglut['rc'] = (29,25) -arglut['imm2'] = (21,20) -arglut['imm3'] = (22,20) -arglut['imm4'] = (23,20) -arglut['imm5'] = (24,20) -arglut['imm6'] = (25,20) - -# for vectors -arglut['vd'] = (11,7) -arglut['vs3'] = (11,7) -arglut['vs1'] = (19,15) -arglut['vs2'] = (24,20) -arglut['vm'] = (25,25) -arglut['wd'] = (26,26) -arglut['amoop'] = (31,27) -arglut['nf'] = (31,29) -arglut['simm5'] = (19,15) -arglut['zimm10'] = (29,20) -arglut['zimm11'] = (30,20) - -# -# Trap cause codes -causes = [ - (0x00, 'misaligned fetch'), - (0x01, 'fetch access'), - (0x02, 'illegal instruction'), - (0x03, 'breakpoint'), - (0x04, 'misaligned load'), - (0x05, 'load access'), - (0x06, 'misaligned store'), - (0x07, 'store access'), - (0x08, 'user_ecall'), - (0x09, 'supervisor_ecall'), - (0x0A, 'virtual_supervisor_ecall'), - (0x0B, 'machine_ecall'), - (0x0C, 'fetch page fault'), - (0x0D, 'load page fault'), - (0x0F, 'store page fault'), - (0x14, 'fetch guest page fault'), - (0x15, 'load guest page fault'), - (0x16, 'virtual instruction'), - (0x17, 'store guest page fault'), -] - -csrs = [ - # Standard User R/W - (0x001, 'fflags'), - (0x002, 'frm'), - (0x003, 'fcsr'), - (0x008, 'vstart'), - (0x009, 'vxsat'), - (0x00A, 'vxrm'), - (0x00F, 'vcsr'), - (0x015, 'seed'), # Zkr - - # Standard User RO - (0xC00, 'cycle'), - (0xC01, 'time'), - (0xC02, 'instret'), - (0xC03, 'hpmcounter3'), - (0xC04, 'hpmcounter4'), - (0xC05, 'hpmcounter5'), - (0xC06, 'hpmcounter6'), - (0xC07, 'hpmcounter7'), - (0xC08, 'hpmcounter8'), - (0xC09, 'hpmcounter9'), - (0xC0A, 'hpmcounter10'), - (0xC0B, 'hpmcounter11'), - (0xC0C, 'hpmcounter12'), - (0xC0D, 'hpmcounter13'), - (0xC0E, 'hpmcounter14'), - (0xC0F, 'hpmcounter15'), - (0xC10, 'hpmcounter16'), - (0xC11, 'hpmcounter17'), - (0xC12, 'hpmcounter18'), - (0xC13, 'hpmcounter19'), - (0xC14, 'hpmcounter20'), - (0xC15, 'hpmcounter21'), - (0xC16, 'hpmcounter22'), - (0xC17, 'hpmcounter23'), - (0xC18, 'hpmcounter24'), - (0xC19, 'hpmcounter25'), - (0xC1A, 'hpmcounter26'), - (0xC1B, 'hpmcounter27'), - (0xC1C, 'hpmcounter28'), - (0xC1D, 'hpmcounter29'), - (0xC1E, 'hpmcounter30'), - (0xC1F, 'hpmcounter31'), - (0xC20, 'vl'), - (0xC21, 'vtype'), - (0xC22, 'vlenb'), - - # Standard Supervisor R/W - (0x100, 'sstatus'), - (0x102, 'sedeleg'), - (0x103, 'sideleg'), - (0x104, 'sie'), - (0x105, 'stvec'), - (0x106, 'scounteren'), - (0x10A, 'senvcfg'), - (0x140, 'sscratch'), - (0x141, 'sepc'), - (0x142, 'scause'), - (0x143, 'stval'), - (0x144, 'sip'), - (0x180, 'satp'), - (0x5A8, 'scontext'), - - # Standard Hypervisor R/w - (0x200, 'vsstatus'), - (0x204, 'vsie'), - (0x205, 'vstvec'), - (0x240, 'vsscratch'), - (0x241, 'vsepc'), - (0x242, 'vscause'), - (0x243, 'vstval'), - (0x244, 'vsip'), - (0x280, 'vsatp'), - (0x600, 'hstatus'), - (0x602, 'hedeleg'), - (0x603, 'hideleg'), - (0x604, 'hie'), - (0x605, 'htimedelta'), - (0x606, 'hcounteren'), - (0x607, 'hgeie'), - (0x60A, 'henvcfg'), - (0x643, 'htval'), - (0x644, 'hip'), - (0x645, 'hvip'), - (0x64A, 'htinst'), - (0x680, 'hgatp'), - (0x6A8, 'hcontext'), - (0xE12, 'hgeip'), - - # Tentative CSR assignment for CLIC - (0x007, 'utvt'), - (0x045, 'unxti'), - (0x046, 'uintstatus'), - (0x048, 'uscratchcsw'), - (0x049, 'uscratchcswl'), - (0x107, 'stvt'), - (0x145, 'snxti'), - (0x146, 'sintstatus'), - (0x148, 'sscratchcsw'), - (0x149, 'sscratchcswl'), - (0x307, 'mtvt'), - (0x345, 'mnxti'), - (0x346, 'mintstatus'), - (0x348, 'mscratchcsw'), - (0x349, 'mscratchcswl'), - - # Standard Machine R/W - (0x300, 'mstatus'), - (0x301, 'misa'), - (0x302, 'medeleg'), - (0x303, 'mideleg'), - (0x304, 'mie'), - (0x305, 'mtvec'), - (0x306, 'mcounteren'), - (0x30a, 'menvcfg'), - (0x320, 'mcountinhibit'), - (0x340, 'mscratch'), - (0x341, 'mepc'), - (0x342, 'mcause'), - (0x343, 'mtval'), - (0x344, 'mip'), - (0x34a, 'mtinst'), - (0x34b, 'mtval2'), - (0x3a0, 'pmpcfg0'), - (0x3a1, 'pmpcfg1'), - (0x3a2, 'pmpcfg2'), - (0x3a3, 'pmpcfg3'), - (0x3a4, 'pmpcfg4'), - (0x3a5, 'pmpcfg5'), - (0x3a6, 'pmpcfg6'), - (0x3a7, 'pmpcfg7'), - (0x3a8, 'pmpcfg8'), - (0x3a9, 'pmpcfg9'), - (0x3aa, 'pmpcfg10'), - (0x3ab, 'pmpcfg11'), - (0x3ac, 'pmpcfg12'), - (0x3ad, 'pmpcfg13'), - (0x3ae, 'pmpcfg14'), - (0x3af, 'pmpcfg15'), - (0x3b0, 'pmpaddr0'), - (0x3b1, 'pmpaddr1'), - (0x3b2, 'pmpaddr2'), - (0x3b3, 'pmpaddr3'), - (0x3b4, 'pmpaddr4'), - (0x3b5, 'pmpaddr5'), - (0x3b6, 'pmpaddr6'), - (0x3b7, 'pmpaddr7'), - (0x3b8, 'pmpaddr8'), - (0x3b9, 'pmpaddr9'), - (0x3ba, 'pmpaddr10'), - (0x3bb, 'pmpaddr11'), - (0x3bc, 'pmpaddr12'), - (0x3bd, 'pmpaddr13'), - (0x3be, 'pmpaddr14'), - (0x3bf, 'pmpaddr15'), - (0x3c0, 'pmpaddr16'), - (0x3c1, 'pmpaddr17'), - (0x3c2, 'pmpaddr18'), - (0x3c3, 'pmpaddr19'), - (0x3c4, 'pmpaddr20'), - (0x3c5, 'pmpaddr21'), - (0x3c6, 'pmpaddr22'), - (0x3c7, 'pmpaddr23'), - (0x3c8, 'pmpaddr24'), - (0x3c9, 'pmpaddr25'), - (0x3ca, 'pmpaddr26'), - (0x3cb, 'pmpaddr27'), - (0x3cc, 'pmpaddr28'), - (0x3cd, 'pmpaddr29'), - (0x3ce, 'pmpaddr30'), - (0x3cf, 'pmpaddr31'), - (0x3d0, 'pmpaddr32'), - (0x3d1, 'pmpaddr33'), - (0x3d2, 'pmpaddr34'), - (0x3d3, 'pmpaddr35'), - (0x3d4, 'pmpaddr36'), - (0x3d5, 'pmpaddr37'), - (0x3d6, 'pmpaddr38'), - (0x3d7, 'pmpaddr39'), - (0x3d8, 'pmpaddr40'), - (0x3d9, 'pmpaddr41'), - (0x3da, 'pmpaddr42'), - (0x3db, 'pmpaddr43'), - (0x3dc, 'pmpaddr44'), - (0x3dd, 'pmpaddr45'), - (0x3de, 'pmpaddr46'), - (0x3df, 'pmpaddr47'), - (0x3e0, 'pmpaddr48'), - (0x3e1, 'pmpaddr49'), - (0x3e2, 'pmpaddr50'), - (0x3e3, 'pmpaddr51'), - (0x3e4, 'pmpaddr52'), - (0x3e5, 'pmpaddr53'), - (0x3e6, 'pmpaddr54'), - (0x3e7, 'pmpaddr55'), - (0x3e8, 'pmpaddr56'), - (0x3e9, 'pmpaddr57'), - (0x3ea, 'pmpaddr58'), - (0x3eb, 'pmpaddr59'), - (0x3ec, 'pmpaddr60'), - (0x3ed, 'pmpaddr61'), - (0x3ee, 'pmpaddr62'), - (0x3ef, 'pmpaddr63'), - (0x747, 'mseccfg'), - (0x7a0, 'tselect'), - (0x7a1, 'tdata1'), - (0x7a2, 'tdata2'), - (0x7a3, 'tdata3'), - (0x7a4, 'tinfo'), - (0x7a5, 'tcontrol'), - (0x7a8, 'mcontext'), - (0x7aa, 'mscontext'), - (0x7b0, 'dcsr'), - (0x7b1, 'dpc'), - (0x7b2, 'dscratch0'), - (0x7b3, 'dscratch1'), - (0xB00, 'mcycle'), - (0xB02, 'minstret'), - (0xB03, 'mhpmcounter3'), - (0xB04, 'mhpmcounter4'), - (0xB05, 'mhpmcounter5'), - (0xB06, 'mhpmcounter6'), - (0xB07, 'mhpmcounter7'), - (0xB08, 'mhpmcounter8'), - (0xB09, 'mhpmcounter9'), - (0xB0A, 'mhpmcounter10'), - (0xB0B, 'mhpmcounter11'), - (0xB0C, 'mhpmcounter12'), - (0xB0D, 'mhpmcounter13'), - (0xB0E, 'mhpmcounter14'), - (0xB0F, 'mhpmcounter15'), - (0xB10, 'mhpmcounter16'), - (0xB11, 'mhpmcounter17'), - (0xB12, 'mhpmcounter18'), - (0xB13, 'mhpmcounter19'), - (0xB14, 'mhpmcounter20'), - (0xB15, 'mhpmcounter21'), - (0xB16, 'mhpmcounter22'), - (0xB17, 'mhpmcounter23'), - (0xB18, 'mhpmcounter24'), - (0xB19, 'mhpmcounter25'), - (0xB1A, 'mhpmcounter26'), - (0xB1B, 'mhpmcounter27'), - (0xB1C, 'mhpmcounter28'), - (0xB1D, 'mhpmcounter29'), - (0xB1E, 'mhpmcounter30'), - (0xB1F, 'mhpmcounter31'), - (0x323, 'mhpmevent3'), - (0x324, 'mhpmevent4'), - (0x325, 'mhpmevent5'), - (0x326, 'mhpmevent6'), - (0x327, 'mhpmevent7'), - (0x328, 'mhpmevent8'), - (0x329, 'mhpmevent9'), - (0x32A, 'mhpmevent10'), - (0x32B, 'mhpmevent11'), - (0x32C, 'mhpmevent12'), - (0x32D, 'mhpmevent13'), - (0x32E, 'mhpmevent14'), - (0x32F, 'mhpmevent15'), - (0x330, 'mhpmevent16'), - (0x331, 'mhpmevent17'), - (0x332, 'mhpmevent18'), - (0x333, 'mhpmevent19'), - (0x334, 'mhpmevent20'), - (0x335, 'mhpmevent21'), - (0x336, 'mhpmevent22'), - (0x337, 'mhpmevent23'), - (0x338, 'mhpmevent24'), - (0x339, 'mhpmevent25'), - (0x33A, 'mhpmevent26'), - (0x33B, 'mhpmevent27'), - (0x33C, 'mhpmevent28'), - (0x33D, 'mhpmevent29'), - (0x33E, 'mhpmevent30'), - (0x33F, 'mhpmevent31'), - - # Standard Machine RO - (0xF11, 'mvendorid'), - (0xF12, 'marchid'), - (0xF13, 'mimpid'), - (0xF14, 'mhartid'), - (0xF15, 'mconfigptr'), -] - -csrs32 = [ - # Standard Hypervisor R/w - (0x615, 'htimedeltah'), - (0x61A, 'henvcfgh'), - - # Standard User RO - (0xC80, 'cycleh'), - (0xC81, 'timeh'), - (0xC82, 'instreth'), - (0xC83, 'hpmcounter3h'), - (0xC84, 'hpmcounter4h'), - (0xC85, 'hpmcounter5h'), - (0xC86, 'hpmcounter6h'), - (0xC87, 'hpmcounter7h'), - (0xC88, 'hpmcounter8h'), - (0xC89, 'hpmcounter9h'), - (0xC8A, 'hpmcounter10h'), - (0xC8B, 'hpmcounter11h'), - (0xC8C, 'hpmcounter12h'), - (0xC8D, 'hpmcounter13h'), - (0xC8E, 'hpmcounter14h'), - (0xC8F, 'hpmcounter15h'), - (0xC90, 'hpmcounter16h'), - (0xC91, 'hpmcounter17h'), - (0xC92, 'hpmcounter18h'), - (0xC93, 'hpmcounter19h'), - (0xC94, 'hpmcounter20h'), - (0xC95, 'hpmcounter21h'), - (0xC96, 'hpmcounter22h'), - (0xC97, 'hpmcounter23h'), - (0xC98, 'hpmcounter24h'), - (0xC99, 'hpmcounter25h'), - (0xC9A, 'hpmcounter26h'), - (0xC9B, 'hpmcounter27h'), - (0xC9C, 'hpmcounter28h'), - (0xC9D, 'hpmcounter29h'), - (0xC9E, 'hpmcounter30h'), - (0xC9F, 'hpmcounter31h'), - - # Standard Machine RW - (0x310, 'mstatush'), - (0x31A, 'menvcfgh'), - (0x757, 'mseccfgh'), - (0xB80, 'mcycleh'), - (0xB82, 'minstreth'), - (0xB83, 'mhpmcounter3h'), - (0xB84, 'mhpmcounter4h'), - (0xB85, 'mhpmcounter5h'), - (0xB86, 'mhpmcounter6h'), - (0xB87, 'mhpmcounter7h'), - (0xB88, 'mhpmcounter8h'), - (0xB89, 'mhpmcounter9h'), - (0xB8A, 'mhpmcounter10h'), - (0xB8B, 'mhpmcounter11h'), - (0xB8C, 'mhpmcounter12h'), - (0xB8D, 'mhpmcounter13h'), - (0xB8E, 'mhpmcounter14h'), - (0xB8F, 'mhpmcounter15h'), - (0xB90, 'mhpmcounter16h'), - (0xB91, 'mhpmcounter17h'), - (0xB92, 'mhpmcounter18h'), - (0xB93, 'mhpmcounter19h'), - (0xB94, 'mhpmcounter20h'), - (0xB95, 'mhpmcounter21h'), - (0xB96, 'mhpmcounter22h'), - (0xB97, 'mhpmcounter23h'), - (0xB98, 'mhpmcounter24h'), - (0xB99, 'mhpmcounter25h'), - (0xB9A, 'mhpmcounter26h'), - (0xB9B, 'mhpmcounter27h'), - (0xB9C, 'mhpmcounter28h'), - (0xB9D, 'mhpmcounter29h'), - (0xB9E, 'mhpmcounter30h'), - (0xB9F, 'mhpmcounter31h'), -] - -opcode_base = 0 -opcode_size = 7 -funct_base = 12 -funct_size = 3 - -def binary(n, digits=0): - rep = bin(n)[2:] - return rep if digits == 0 else ('0' * (digits - len(rep))) + rep - -def make_c(match,mask): - print('/* Automatically generated by parse_opcodes. */') - print('#ifndef RISCV_ENCODING_H') - print('#define RISCV_ENCODING_H') - for name in namelist: - name2 = name.upper().replace('.','_') - print('#define MATCH_%s %s' % (name2, hex(match[name]))) - print('#define MASK_%s %s' % (name2, hex(mask[name]))) - for num, name in csrs+csrs32: - print('#define CSR_%s %s' % (name.upper(), hex(num))) - for num, name in causes: - print('#define CAUSE_%s %s' % (name.upper().replace(' ', '_'), hex(num))) - print('#endif') - - print('#ifdef DECLARE_INSN') - for name in namelist: - name2 = name.replace('.','_') - print('DECLARE_INSN(%s, MATCH_%s, MASK_%s)' % (name2, name2.upper(), name2.upper())) - print('#endif') # #ifdef DECLARE_INSN - - print('#ifdef DECLARE_CSR') - for num, name in csrs+csrs32: - print('DECLARE_CSR(%s, CSR_%s)' % (name, name.upper())) - print('#endif') - - print('#ifdef DECLARE_CAUSE') - for num, name in causes: - print('DECLARE_CAUSE("%s", CAUSE_%s)' % (name, name.upper().replace(' ', '_'))) - print('#endif') - -def yank(num,start,len): - return (num >> start) & ((1 << len) - 1) - -def str_arg(arg0,name,match,arguments): - if arg0 in arguments: - return name or arg0 - else: - start = arglut[arg0][1] - len = arglut[arg0][0] - arglut[arg0][1] + 1 - return binary(yank(match,start,len),len) - -def str_inst(name,arguments): - return name.replace('.rv32','').upper() - -def print_unimp_type(name,match,arguments): - print(""" -& -\\multicolumn{10}{|c|}{%s} & %s \\\\ -\\cline{2-11} -""" % \ - ( \ - '0'*32, \ - 'UNIMP' \ - )) - -def print_u_type(name,match,arguments): - print(""" -& -\\multicolumn{8}{|c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & %s \\\\ -\\cline{2-11} -""" % \ - ( \ - str_arg('imm20','imm[31:12]',match,arguments), \ - str_arg('rd','',match,arguments), \ - binary(yank(match,opcode_base,opcode_size),opcode_size), \ - str_inst(name,arguments) \ - )) - -def print_uj_type(name,match,arguments): - print(""" -& -\\multicolumn{8}{|c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & %s \\\\ -\\cline{2-11} -""" % \ - ( \ - str_arg('jimm20','imm[20$\\vert$10:1$\\vert$11$\\vert$19:12]',match,arguments), \ - str_arg('rd','',match,arguments), \ - binary(yank(match,opcode_base,opcode_size),opcode_size), \ - str_inst(name,arguments) \ - )) - -def print_s_type(name,match,arguments): - print(""" -& -\\multicolumn{4}{|c|}{%s} & -\\multicolumn{2}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & %s \\\\ -\\cline{2-11} -""" % \ - ( \ - str_arg('imm12hi','imm[11:5]',match,arguments), \ - str_arg('rs2','',match,arguments), \ - str_arg('rs1','',match,arguments), \ - binary(yank(match,funct_base,funct_size),funct_size), \ - str_arg('imm12lo','imm[4:0]',match,arguments), \ - binary(yank(match,opcode_base,opcode_size),opcode_size), \ - str_inst(name,arguments) \ - )) - -def print_sb_type(name,match,arguments): - print(""" -& -\\multicolumn{4}{|c|}{%s} & -\\multicolumn{2}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & %s \\\\ -\\cline{2-11} -""" % \ - ( \ - str_arg('bimm12hi','imm[12$\\vert$10:5]',match,arguments), \ - str_arg('rs2','',match,arguments), \ - str_arg('rs1','',match,arguments), \ - binary(yank(match,funct_base,funct_size),funct_size), \ - str_arg('bimm12lo','imm[4:1$\\vert$11]',match,arguments), \ - binary(yank(match,opcode_base,opcode_size),opcode_size), \ - str_inst(name,arguments) \ - )) - -def print_i_type(name,match,arguments): - print(""" -& -\\multicolumn{6}{|c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & %s \\\\ -\\cline{2-11} -""" % \ - ( \ - str_arg('imm12','imm[11:0]',match,arguments), \ - str_arg('rs1','',match,arguments), \ - binary(yank(match,funct_base,funct_size),funct_size), \ - str_arg('rd','',match,arguments), \ - binary(yank(match,opcode_base,opcode_size),opcode_size), \ - str_inst(name,arguments) \ - )) - -def print_csr_type(name,match,arguments): - print(""" -& -\\multicolumn{6}{|c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & %s \\\\ -\\cline{2-11} -""" % \ - ( \ - str_arg('imm12','csr',match,arguments), \ - ('uimm' if name[-1] == 'i' else 'rs1'), \ - binary(yank(match,funct_base,funct_size),funct_size), \ - str_arg('rd','',match,arguments), \ - binary(yank(match,opcode_base,opcode_size),opcode_size), \ - str_inst(name,arguments) \ - )) - -def print_ish_type(name,match,arguments): - print(""" -& -\\multicolumn{3}{|c|}{%s} & -\\multicolumn{3}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & %s \\\\ -\\cline{2-11} -""" % \ - ( \ - binary(yank(match,26,6),6), \ - str_arg('shamt','shamt',match,arguments), \ - str_arg('rs1','',match,arguments), \ - binary(yank(match,funct_base,funct_size),funct_size), \ - str_arg('rd','',match,arguments), \ - binary(yank(match,opcode_base,opcode_size),opcode_size), \ - str_inst(name,arguments) \ - )) - -def print_ishw_type(name,match,arguments): - print(""" -& -\\multicolumn{4}{|c|}{%s} & -\\multicolumn{2}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & %s \\\\ -\\cline{2-11} -""" % \ - ( \ - binary(yank(match,25,7),7), \ - str_arg('shamtw','shamt',match,arguments), \ - str_arg('rs1','',match,arguments), \ - binary(yank(match,funct_base,funct_size),funct_size), \ - str_arg('rd','',match,arguments), \ - binary(yank(match,opcode_base,opcode_size),opcode_size), \ - str_inst(name,arguments) \ - )) - -def print_r_type(name,match,arguments): - print(""" -& -\\multicolumn{4}{|c|}{%s} & -\\multicolumn{2}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & %s \\\\ -\\cline{2-11} -""" % \ - ( \ - binary(yank(match,25,7),7), \ - str_arg('rs2','',match,arguments), \ - 'zimm' in arguments and str_arg('zimm','imm[4:0]',match,arguments) or str_arg('rs1','',match,arguments), \ - str_arg('rm','',match,arguments), \ - str_arg('rd','',match,arguments), \ - binary(yank(match,opcode_base,opcode_size),opcode_size), \ - str_inst(name,arguments) \ - )) - -def print_r4_type(name,match,arguments): - print(""" -& -\\multicolumn{2}{|c|}{%s} & -\\multicolumn{2}{c|}{%s} & -\\multicolumn{2}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & %s \\\\ -\\cline{2-11} -""" % \ - ( \ - str_arg('rs3','',match,arguments), \ - binary(yank(match,25,2),2), \ - str_arg('rs2','',match,arguments), \ - str_arg('rs1','',match,arguments), \ - str_arg('rm','',match,arguments), \ - str_arg('rd','',match,arguments), \ - binary(yank(match,opcode_base,opcode_size),opcode_size), \ - str_inst(name,arguments) \ - )) - -def print_amo_type(name,match,arguments): - print(""" -& -\\multicolumn{2}{|c|}{%s} & -\\multicolumn{1}{c|}{aq} & -\\multicolumn{1}{c|}{rl} & -\\multicolumn{2}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & %s \\\\ -\\cline{2-11} -""" % \ - ( \ - binary(yank(match,27,5),5), \ - str_arg('rs2','',match,arguments), \ - str_arg('rs1','',match,arguments), \ - binary(yank(match,funct_base,funct_size),funct_size), \ - str_arg('rd','',match,arguments), \ - binary(yank(match,opcode_base,opcode_size),opcode_size), \ - str_inst(name,arguments) \ - )) - -def print_fence_type(name,match,arguments): - print(""" -& -\\multicolumn{2}{|c|}{%s} & -\\multicolumn{3}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & -\\multicolumn{1}{c|}{%s} & %s \\\\ -\\cline{2-11} -""" % \ - ( \ - str_arg('fm','fm',match,arguments), \ - str_arg('pred','pred',match,arguments), \ - str_arg('succ','',match,arguments), \ - str_arg('rs1','',match,arguments), \ - binary(yank(match,funct_base,funct_size),funct_size), \ - str_arg('rd','',match,arguments), \ - binary(yank(match,opcode_base,opcode_size),opcode_size), \ - str_inst(name,arguments) \ - )) - -def print_header(*types): - print(""" -\\newpage - -\\begin{table}[p] -\\begin{small} -\\begin{center} -\\begin{tabular}{p{0in}p{0.4in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.4in}p{0.6in}p{0.4in}p{0.6in}p{0.7in}l} -& & & & & & & & & & \\\\ - & -\\multicolumn{1}{l}{\\instbit{31}} & -\\multicolumn{1}{r}{\\instbit{27}} & -\\instbit{26} & -\\instbit{25} & -\\multicolumn{1}{l}{\\instbit{24}} & -\\multicolumn{1}{r}{\\instbit{20}} & -\\instbitrange{19}{15} & -\\instbitrange{14}{12} & -\\instbitrange{11}{7} & -\\instbitrange{6}{0} \\\\ -\\cline{2-11} -""") - if 'r' in types: - print(""" -& -\\multicolumn{4}{|c|}{funct7} & -\\multicolumn{2}{c|}{rs2} & -\\multicolumn{1}{c|}{rs1} & -\\multicolumn{1}{c|}{funct3} & -\\multicolumn{1}{c|}{rd} & -\\multicolumn{1}{c|}{opcode} & R-type \\\\ -\\cline{2-11} -""") - if 'r4' in types: - print(""" -& -\\multicolumn{2}{|c|}{rs3} & -\\multicolumn{2}{c|}{funct2} & -\\multicolumn{2}{c|}{rs2} & -\\multicolumn{1}{c|}{rs1} & -\\multicolumn{1}{c|}{funct3} & -\\multicolumn{1}{c|}{rd} & -\\multicolumn{1}{c|}{opcode} & R4-type \\\\ -\\cline{2-11} -""") - if 'i' in types: - print(""" -& -\\multicolumn{6}{|c|}{imm[11:0]} & -\\multicolumn{1}{c|}{rs1} & -\\multicolumn{1}{c|}{funct3} & -\\multicolumn{1}{c|}{rd} & -\\multicolumn{1}{c|}{opcode} & I-type \\\\ -\\cline{2-11} -""") - if 's' in types: - print(""" -& -\\multicolumn{4}{|c|}{imm[11:5]} & -\\multicolumn{2}{c|}{rs2} & -\\multicolumn{1}{c|}{rs1} & -\\multicolumn{1}{c|}{funct3} & -\\multicolumn{1}{c|}{imm[4:0]} & -\\multicolumn{1}{c|}{opcode} & S-type \\\\ -\\cline{2-11} -""") - if 'sb' in types: - print(""" -& -\\multicolumn{4}{|c|}{imm[12$\\vert$10:5]} & -\\multicolumn{2}{c|}{rs2} & -\\multicolumn{1}{c|}{rs1} & -\\multicolumn{1}{c|}{funct3} & -\\multicolumn{1}{c|}{imm[4:1$\\vert$11]} & -\\multicolumn{1}{c|}{opcode} & B-type \\\\ -\\cline{2-11} -""") - if 'u' in types: - print(""" -& -\\multicolumn{8}{|c|}{imm[31:12]} & -\\multicolumn{1}{c|}{rd} & -\\multicolumn{1}{c|}{opcode} & U-type \\\\ -\\cline{2-11} -""") - if 'uj' in types: - print(""" -& -\\multicolumn{8}{|c|}{imm[20$\\vert$10:1$\\vert$11$\\vert$19:12]} & -\\multicolumn{1}{c|}{rd} & -\\multicolumn{1}{c|}{opcode} & J-type \\\\ -\\cline{2-11} -""") - -def print_subtitle(title): - print(""" -& -\\multicolumn{10}{c}{} & \\\\ -& -\\multicolumn{10}{c}{\\bf %s} & \\\\ -\\cline{2-11} -""" % title) - -def print_footer(caption=''): - print(""" -\\end{tabular} -\\end{center} -\\end{small} -%s -\\end{table} -""" % caption) - -def print_inst(n): - if n == 'fence' or n == 'fence.tso' or n == 'pause': - print_fence_type(n, match[n], arguments[n]) - elif 'aqrl' in arguments[n]: - print_amo_type(n, match[n], arguments[n]) - elif 'shamt' in arguments[n]: - print_ish_type(n, match[n], arguments[n]) - elif 'shamtw' in arguments[n]: - print_ishw_type(n, match[n], arguments[n]) - elif 'imm20' in arguments[n]: - print_u_type(n, match[n], arguments[n]) - elif 'jimm20' in arguments[n]: - print_uj_type(n, match[n], arguments[n]) - elif n[:3] == 'csr': - print_csr_type(n, match[n], arguments[n]) - elif 'imm12' in arguments[n] or n == 'ecall' or n == 'ebreak': - print_i_type(n, match[n], arguments[n]) - elif 'imm12hi' in arguments[n]: - print_s_type(n, match[n], arguments[n]) - elif 'bimm12hi' in arguments[n]: - print_sb_type(n, match[n], arguments[n]) - elif 'rs3' in arguments[n]: - print_r4_type(n, match[n], arguments[n]) - else: - print_r_type(n, match[n], arguments[n]) - -def print_insts(*names): - for n in names: - print_inst(n) - -def make_supervisor_latex_table(): - print_header('r', 'i') - print_subtitle('Trap-Return Instructions') - print_insts('sret', 'mret') - print_subtitle('Interrupt-Management Instructions') - print_insts('wfi') - print_subtitle('Supervisor Memory-Management Instructions') - print_insts('sfence.vma') - print_subtitle('Hypervisor Memory-Management Instructions') - print_insts('hfence.vvma', 'hfence.gvma') - print_subtitle('Hypervisor Virtual-Machine Load and Store Instructions') - print_insts('hlv.b', 'hlv.bu') - print_insts('hlv.h', 'hlv.hu') - print_insts('hlv.w') - print_insts('hlvx.hu', 'hlvx.wu') - print_insts('hsv.b', 'hsv.h', 'hsv.w') - print_subtitle('Hypervisor Virtual-Machine Load and Store Instructions, RV64 only') - print_insts('hlv.wu') - print_insts('hlv.d') - print_insts('hsv.d') - print_subtitle('\emph{Svinval} Memory-Management Extension') - print_insts('sinval.vma') - print_insts('sfence.w.inval', 'sfence.inval.ir') - print_insts('hinval.vvma', 'hinval.gvma') - print_footer('\\caption{RISC-V Privileged Instructions}') - -def make_latex_table(): - print_header('r','i','s','sb','u','uj') - print_subtitle('RV32I Base Instruction Set') - print_insts('lui', 'auipc') - print_insts('jal', 'jalr', 'beq', 'bne', 'blt', 'bge', 'bltu', 'bgeu') - print_insts('lb', 'lh', 'lw', 'lbu', 'lhu', 'sb', 'sh', 'sw') - print_insts('addi', 'slti', 'sltiu', 'xori', 'ori', 'andi', 'slli.rv32', 'srli.rv32', 'srai.rv32') - print_insts('add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and') - print_insts('fence', 'fence.tso', 'pause') - print_insts('ecall', 'ebreak') - print_footer() - - print_header('r','a','i','s') - print_subtitle('RV64I Base Instruction Set (in addition to RV32I)') - print_insts('lwu', 'ld', 'sd') - print_insts('slli', 'srli', 'srai') - print_insts('addiw', 'slliw', 'srliw', 'sraiw') - print_insts('addw', 'subw', 'sllw', 'srlw', 'sraw') - print_subtitle('RV32/RV64 \emph{Zifencei} Standard Extension') - print_insts('fence.i') - print_subtitle('RV32/RV64 \emph{Zicsr} Standard Extension') - print_insts('csrrw', 'csrrs', 'csrrc') - print_insts('csrrwi', 'csrrsi', 'csrrci') - print_subtitle('RV32M Standard Extension') - print_insts('mul', 'mulh', 'mulhsu', 'mulhu') - print_insts('div', 'divu', 'rem', 'remu') - print_subtitle('RV64M Standard Extension (in addition to RV32M)') - print_insts('mulw', 'divw', 'divuw', 'remw', 'remuw') - print_footer() - - print_header('r') - print_subtitle('RV32A Standard Extension') - print_insts('lr.w', 'sc.w') - print_insts('amoswap.w') - print_insts('amoadd.w', 'amoxor.w', 'amoand.w', 'amoor.w') - print_insts('amomin.w', 'amomax.w', 'amominu.w', 'amomaxu.w') - print_subtitle('RV64A Standard Extension (in addition to RV32A)') - print_insts('lr.d', 'sc.d') - print_insts('amoswap.d') - print_insts('amoadd.d', 'amoxor.d', 'amoand.d', 'amoor.d') - print_insts('amomin.d', 'amomax.d', 'amominu.d', 'amomaxu.d') - print_subtitle('RV32/RV64 \emph{Zicbom} Standard Extension') - print_insts('cbo.clean') - print_insts('cbo.flush') - print_insts('cbo.inval') - print_subtitle('RV32/RV64 \emph{Zicboz} Standard Extension') - print_insts('cbo.zero') - print_subtitle('RV32/RV64 \emph{Zicbop} Standard Extension') - print_insts('prefetch.i', 'prefetch.r', 'prefetch.w') - print_footer() - - print_header('r','r4','i','s') - print_subtitle('RV32F Standard Extension') - print_insts('flw', 'fsw') - print_insts('fmadd.s', 'fmsub.s', 'fnmsub.s', 'fnmadd.s') - print_insts('fadd.s', 'fsub.s', 'fmul.s', 'fdiv.s', 'fsqrt.s') - print_insts('fsgnj.s', 'fsgnjn.s', 'fsgnjx.s', 'fmin.s', 'fmax.s') - print_insts('fcvt.w.s', 'fcvt.wu.s', 'fmv.x.w') - print_insts('feq.s', 'flt.s', 'fle.s', 'fclass.s') - print_insts('fcvt.s.w', 'fcvt.s.wu', 'fmv.w.x') - print_subtitle('RV64F Standard Extension (in addition to RV32F)') - print_insts('fcvt.l.s', 'fcvt.lu.s') - print_insts('fcvt.s.l', 'fcvt.s.lu') - print_footer() - - print_header('r','r4','i','s') - print_subtitle('RV32D Standard Extension') - print_insts('fld', 'fsd') - print_insts('fmadd.d', 'fmsub.d', 'fnmsub.d', 'fnmadd.d') - print_insts('fadd.d', 'fsub.d', 'fmul.d', 'fdiv.d', 'fsqrt.d') - print_insts('fsgnj.d', 'fsgnjn.d', 'fsgnjx.d', 'fmin.d', 'fmax.d') - print_insts('fcvt.s.d', 'fcvt.d.s') - print_insts('feq.d', 'flt.d', 'fle.d', 'fclass.d') - print_insts('fcvt.w.d', 'fcvt.wu.d') - print_insts('fcvt.d.w', 'fcvt.d.wu') - print_subtitle('RV64D Standard Extension (in addition to RV32D)') - print_insts('fcvt.l.d', 'fcvt.lu.d', 'fmv.x.d') - print_insts('fcvt.d.l', 'fcvt.d.lu', 'fmv.d.x') - print_footer() - - print_header('r','r4','i','s') - print_subtitle('RV32Q Standard Extension') - print_insts('flq', 'fsq') - print_insts('fmadd.q', 'fmsub.q', 'fnmsub.q', 'fnmadd.q') - print_insts('fadd.q', 'fsub.q', 'fmul.q', 'fdiv.q', 'fsqrt.q') - print_insts('fsgnj.q', 'fsgnjn.q', 'fsgnjx.q', 'fmin.q', 'fmax.q') - print_insts('fcvt.s.q', 'fcvt.q.s') - print_insts('fcvt.d.q', 'fcvt.q.d') - print_insts('feq.q', 'flt.q', 'fle.q', 'fclass.q') - print_insts('fcvt.w.q', 'fcvt.wu.q') - print_insts('fcvt.q.w', 'fcvt.q.wu') - print_subtitle('RV64Q Standard Extension (in addition to RV32Q)') - print_insts('fcvt.l.q', 'fcvt.lu.q') - print_insts('fcvt.q.l', 'fcvt.q.lu') - print_footer() - - print_header('r','r4','i','s') - print_subtitle('RV32Zfh Standard Extension') - print_insts('flh', 'fsh') - print_insts('fmadd.h', 'fmsub.h', 'fnmsub.h', 'fnmadd.h') - print_insts('fadd.h', 'fsub.h', 'fmul.h', 'fdiv.h', 'fsqrt.h') - print_insts('fsgnj.h', 'fsgnjn.h', 'fsgnjx.h', 'fmin.h', 'fmax.h') - print_insts('fcvt.s.h', 'fcvt.h.s') - print_insts('fcvt.d.h', 'fcvt.h.d') - print_insts('fcvt.q.h', 'fcvt.h.q') - print_insts('feq.h', 'flt.h', 'fle.h', 'fclass.h') - print_insts('fcvt.w.h', 'fcvt.wu.h', 'fmv.x.h') - print_insts('fcvt.h.w', 'fcvt.h.wu', 'fmv.h.x') - print_subtitle('RV64Zfh Standard Extension (in addition to RV32Zfh)') - print_insts('fcvt.l.h', 'fcvt.lu.h') - print_insts('fcvt.h.l', 'fcvt.h.lu') - print_footer('\\caption{Instruction listing for RISC-V}') - -def print_chisel_insn(name): - s = " def %-18s = BitPat(\"b" % name.replace('.', '_').upper() - for i in range(31, -1, -1): - if yank(mask[name], i, 1): - s = '%s%d' % (s, yank(match[name], i, 1)) - else: - s = s + '?' - print(s + "\")") - -def make_chisel(): - print('/* Automatically generated by parse_opcodes */') - print('object Instructions {') - for name in namelist: - print_chisel_insn(name) - print('}') - print('object Causes {') - for num, name in causes: - print(' val %s = %s' % (name.lower().replace(' ', '_'), hex(num))) - print(' val all = {') - print(' val res = collection.mutable.ArrayBuffer[Int]()') - for num, name in causes: - print(' res += %s' % (name.lower().replace(' ', '_'))) - print(' res.toArray') - print(' }') - print('}') - print('object CSRs {') - for num, name in csrs+csrs32: - print(' val %s = %s' % (name, hex(num))) - print(' val all = {') - print(' val res = collection.mutable.ArrayBuffer[Int]()') - for num, name in csrs: - print(' res += %s' % (name)) - print(' res.toArray') - print(' }') - print(' val all32 = {') - print(' val res = collection.mutable.ArrayBuffer(all:_*)') - for num, name in csrs32: - print(' res += %s' % (name)) - print(' res.toArray') - print(' }') - print('}') - -def print_sverilog_insn(name): - s = " localparam [31:0] %-18s = 32'b" % name.replace('.', '_').upper() - for i in range(31, -1, -1): - if yank(mask[name], i, 1): - s = '%s%d' % (s, yank(match[name], i, 1)) - else: - s = s + '?' - print(s + ";") - -def make_sverilog(): - print('/* Automatically generated by parse_opcodes */') - print('package riscv_instr;') - for name in namelist: - print_sverilog_insn(name) - print(' /* CSR Addresses */') - for num, name in csrs+csrs32: - print(' localparam logic [11:0] CSR_%s = 12\'h%s;' % (name.upper(), hex(num)[2:])) - print('endpackage') - -def signed(value, width): - if 0 <= value < (1<<(width-1)): - return value - else: - return value - (1<= 2 - - name = tokens[0] - pseudo = name[0] == '@' - if pseudo: - name = name[1:] - mymatch = 0 - mymask = 0 - cover = 0 - - if not name in list(arguments.keys()): - arguments[name] = [] - - for token in tokens[1:]: - if len(token.split('=')) == 2: - tokens = token.split('=') - if len(tokens[0].split('..')) == 2: - tmp = tokens[0].split('..') - hi = int(tmp[0]) - lo = int(tmp[1]) - if hi <= lo: - sys.exit("%s: bad range %d..%d" % (name,hi,lo)) - else: - hi = lo = int(tokens[0]) - - if tokens[1] != 'ignore': - val = int(tokens[1], 0) - if val >= (1 << (hi-lo+1)): - sys.exit("%s: bad value %d for range %d..%d" % (name,val,hi,lo)) - mymatch = mymatch | (val << lo) - mymask = mymask | ((1<<(hi+1))-(1< Date: Fri, 8 Apr 2022 21:34:34 +0530 Subject: change xperm.[nbhw] to xperm[4,8,16,32] - this changes the imports in zk[ns] - this name is also what spike uses for now. - This fix may come-back later when zbp and zbkx reconcile on a common naming scheme for these instructions. --- rv_zbkx | 4 ++-- rv_zk | 4 ++-- rv_zkn | 4 ++-- rv_zks | 4 ++-- unratified/rv64_zbp | 2 +- unratified/rv_zbp | 6 +++--- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/rv_zbkx b/rv_zbkx index 12bc0b4..f6b64d9 100644 --- a/rv_zbkx +++ b/rv_zbkx @@ -1,2 +1,2 @@ -xperm4 rd rs1 rs2 31..25=20 14..12=2 6..2=0x0C 1..0=3 -xperm8 rd rs1 rs2 31..25=20 14..12=4 6..2=0x0C 1..0=3 +$import rv_zbp::xperm4 +$import rv_zbp::xperm8 diff --git a/rv_zk b/rv_zk index bdd8514..c4dc854 100644 --- a/rv_zk +++ b/rv_zk @@ -13,8 +13,8 @@ $import rv_zbc::clmul $import rv_zbc::clmulh #import zbkx -$import rv_zbkx::xperm4 -$import rv_zbkx::xperm8 +$import rv_zbp::xperm4 +$import rv_zbp::xperm8 #import zknh # Scalar SHA256 - RV32/RV64 diff --git a/rv_zkn b/rv_zkn index bdd8514..c4dc854 100644 --- a/rv_zkn +++ b/rv_zkn @@ -13,8 +13,8 @@ $import rv_zbc::clmul $import rv_zbc::clmulh #import zbkx -$import rv_zbkx::xperm4 -$import rv_zbkx::xperm8 +$import rv_zbp::xperm4 +$import rv_zbp::xperm8 #import zknh # Scalar SHA256 - RV32/RV64 diff --git a/rv_zks b/rv_zks index 20516f3..f88a09b 100644 --- a/rv_zks +++ b/rv_zks @@ -13,8 +13,8 @@ $import rv_zbc::clmul $import rv_zbc::clmulh #import zbkx -$import rv_zbkx::xperm4 -$import rv_zbkx::xperm8 +$import rv_zbp::xperm4 +$import rv_zbp::xperm8 # Scalar SM4 - RV32, RV64 $import rv_zksed::sm4ed diff --git a/unratified/rv64_zbp b/unratified/rv64_zbp index f4c0bca..f8c06bd 100644 --- a/unratified/rv64_zbp +++ b/unratified/rv64_zbp @@ -14,4 +14,4 @@ gorciw rd rs1 31..26=10 25=0 shamtw 14..12=5 6..2=0x06 1..0=3 greviw rd rs1 31..26=26 25=0 shamtw 14..12=5 6..2=0x06 1..0=3 shflw rd rs1 rs2 31..25=4 14..12=1 6..2=0x0E 1..0=3 unshflw rd rs1 rs2 31..25=4 14..12=5 6..2=0x0E 1..0=3 -xperm.w rd rs1 rs2 31..25=20 14..12=0 6..2=0x0C 1..0=3 +xperm32 rd rs1 rs2 31..25=20 14..12=0 6..2=0x0C 1..0=3 diff --git a/unratified/rv_zbp b/unratified/rv_zbp index 810fe9d..b66d6b4 100644 --- a/unratified/rv_zbp +++ b/unratified/rv_zbp @@ -9,7 +9,7 @@ grev rd rs1 rs2 31..25=52 14..12=5 6..2=0x0C 1..0=3 gorc rd rs1 rs2 31..25=20 14..12=5 6..2=0x0C 1..0=3 shfl rd rs1 rs2 31..25=4 14..12=1 6..2=0x0C 1..0=3 unshfl rd rs1 rs2 31..25=4 14..12=5 6..2=0x0C 1..0=3 -xperm.n rd rs1 rs2 31..25=20 14..12=2 6..2=0x0C 1..0=3 -xperm.b rd rs1 rs2 31..25=20 14..12=4 6..2=0x0C 1..0=3 -xperm.h rd rs1 rs2 31..25=20 14..12=6 6..2=0x0C 1..0=3 +xperm4 rd rs1 rs2 31..25=20 14..12=2 6..2=0x0C 1..0=3 +xperm8 rd rs1 rs2 31..25=20 14..12=4 6..2=0x0C 1..0=3 +xperm16 rd rs1 rs2 31..25=20 14..12=6 6..2=0x0C 1..0=3 packu rd rs1 rs2 31..25=36 14..12=4 6..2=0x0C 1..0=3 -- cgit v1.1 From 1ad98bac0c4e0264b962e95f4b52a2591ba8ec74 Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Fri, 8 Apr 2022 22:19:32 +0530 Subject: pass only fence_tso and pause to rv32i latex table --- parse.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/parse.py b/parse.py index 970c29d..4ae4a51 100755 --- a/parse.py +++ b/parse.py @@ -409,7 +409,8 @@ def make_latex_table(): # instructions listed in list_of_instructions will be dumped into latex. caption = '' type_list = ['R-type','I-type','S-type','B-type','U-type','J-type'] - dataset_list = [(['_i','32_i'], 'RV32I Base Instruction Set', [], True)] + dataset_list = [(['_i','32_i'], 'RV32I Base Instruction Set', [], False)] + dataset_list.append((['_i'], '', ['fence_tso','pause'], True)) make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) type_list = ['R-type','I-type','S-type'] -- cgit v1.1 From bcf0a019a5ab6c467acd39147ced59ca0d0b4852 Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Mon, 11 Apr 2022 11:30:45 +0530 Subject: migrate V-extension aliases --- opcodes-rvv-pseudo | 18 ------------------ rv_v_aliases | 18 ++++++++++++++++++ 2 files changed, 18 insertions(+), 18 deletions(-) delete mode 100644 opcodes-rvv-pseudo create mode 100644 rv_v_aliases diff --git a/opcodes-rvv-pseudo b/opcodes-rvv-pseudo deleted file mode 100644 index 35cf095..0000000 --- a/opcodes-rvv-pseudo +++ /dev/null @@ -1,18 +0,0 @@ -# vmv1r.v, vmv2r.v, vmv4r.v, vmv8r.v -@vmvnfr.v 31..26=0x27 25=1 vs2 simm5 14..12=0x3 vd 6..0=0x57 - -@vl1r.v 31..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 -@vl2r.v 31..26=1 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 -@vl4r.v 31..26=3 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 -@vl8r.v 31..26=7 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 - -@vle1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vd 6..0=0x07 -@vse1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vs3 6..0=0x27 - -@vfredsum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -@vfwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 - -@vpopc.m 31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57 - -@vmornot.mm 31..26=0x1c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -@vmandnot.mm 31..26=0x18 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 diff --git a/rv_v_aliases b/rv_v_aliases new file mode 100644 index 0000000..0f7aaa6 --- /dev/null +++ b/rv_v_aliases @@ -0,0 +1,18 @@ +# vmv1r.v, vmv2r.v, vmv4r.v, vmv8r.v +#@vmvnfr.v 31..26=0x27 25=1 vs2 simm5 14..12=0x3 vd 6..0=0x57 + +$pseudo_op rv_v::vl1re8.v vl1r.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +$pseudo_op rv_v::vl2re8.v vl2r.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +$pseudo_op rv_v::vl4re8.v vl4r.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +$pseudo_op rv_v::vl8re8.v vl8r.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 + +$pseudo_op rv_v::vlm.v vle1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vd 6..0=0x07 +$pseudo_op rv_v::vsm.v vse1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vs3 6..0=0x27 + +$pseudo_op rv_v::vfredusum.vs vfredsum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +$pseudo_op rv_v::vfwredusum.vs vfwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 + +$pseudo_op rv_v::vcpop.m vpopc.m 31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57 + +$pseudo_op rv_v::vmorn.mm vmornot.mm 31..26=0x1c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +$pseudo_op rv_v::vmandn.mm vmandnot.mm 31..26=0x18 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -- cgit v1.1 From d8552e5bd23e9dec802579f3f7c76d137eaca42c Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Mon, 11 Apr 2022 11:31:18 +0530 Subject: update github actions yaml with new command line --- .github/workflows/python-app.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/python-app.yml b/.github/workflows/python-app.yml index e259c3e..798c25f 100644 --- a/.github/workflows/python-app.yml +++ b/.github/workflows/python-app.yml @@ -16,6 +16,6 @@ jobs: with: python-version: 3.8 - name: Generation C code - run: cat opcodes-* | ./parse_opcodes -c > result.h + run: ./parse.py -c -chisel -sverilog -rust -latex "rv*" "unratified/rv*" - name: Check C output - run: cat result.h | cpp + run: cat encoding.out.h | cpp -- cgit v1.1 From c02c9999ec16a45ed49d64b1c259c202dcc3254e Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Mon, 11 Apr 2022 14:25:03 +0530 Subject: remove custom opcodes see #106 --- opcodes-custom | 27 --------------------------- 1 file changed, 27 deletions(-) delete mode 100644 opcodes-custom diff --git a/opcodes-custom b/opcodes-custom deleted file mode 100644 index 1df6f0f..0000000 --- a/opcodes-custom +++ /dev/null @@ -1,27 +0,0 @@ -@custom0 rd rs1 imm12 14..12=0 6..2=0x02 1..0=3 -@custom0.rs1 rd rs1 imm12 14..12=2 6..2=0x02 1..0=3 -@custom0.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x02 1..0=3 -@custom0.rd rd rs1 imm12 14..12=4 6..2=0x02 1..0=3 -@custom0.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x02 1..0=3 -@custom0.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x02 1..0=3 - -@custom1 rd rs1 imm12 14..12=0 6..2=0x0A 1..0=3 -@custom1.rs1 rd rs1 imm12 14..12=2 6..2=0x0A 1..0=3 -@custom1.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x0A 1..0=3 -@custom1.rd rd rs1 imm12 14..12=4 6..2=0x0A 1..0=3 -@custom1.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x0A 1..0=3 -@custom1.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x0A 1..0=3 - -@custom2 rd rs1 imm12 14..12=0 6..2=0x16 1..0=3 -@custom2.rs1 rd rs1 imm12 14..12=2 6..2=0x16 1..0=3 -@custom2.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x16 1..0=3 -@custom2.rd rd rs1 imm12 14..12=4 6..2=0x16 1..0=3 -@custom2.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x16 1..0=3 -@custom2.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x16 1..0=3 - -@custom3 rd rs1 imm12 14..12=0 6..2=0x1E 1..0=3 -@custom3.rs1 rd rs1 imm12 14..12=2 6..2=0x1E 1..0=3 -@custom3.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x1E 1..0=3 -@custom3.rd rd rs1 imm12 14..12=4 6..2=0x1E 1..0=3 -@custom3.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x1E 1..0=3 -@custom3.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x1E 1..0=3 -- cgit v1.1 From 314d83dc5a96e1091d897e67e09e0ca25aa72a1a Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Mon, 2 May 2022 18:16:11 +0530 Subject: adding backward compatible makefile targets --- Makefile | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/Makefile b/Makefile index 828916f..b8cd4db 100644 --- a/Makefile +++ b/Makefile @@ -7,28 +7,31 @@ INSTALL_HEADER_FILES := $(ISASIM_H) $(PK_H) $(ENV_H) $(OPENOCD_H) default: everything +install: everything + set -e; for FILE in $(INSTALL_HEADER_FILES); do cp -f encoding.out.h $$FILE; done + .PHONY : everything everything: @./parse.py -c -chisel -sverilog -rust -latex $(EXTENSIONS) -.PHONY : c -c: +.PHONY : encoding.out.h +encoding.out.h: @./parse.py -c $(EXTENSIONS) -.PHONY : chisel -chisel: +.PHONY : inst.chisel +inst.chisel: @./parse.py -chisel $(EXTENSIONS) .PHONY : latex latex: @./parse.py -latex $(EXTENSIONS) -.PHONY : sverilog -sverilog: +.PHONY : inst.sverilog +inst.sverilog: @./parse.py -sverilog $(EXTENSIONS) -.PHONY : rust -rust: +.PHONY : inst.rs +inst.rs: @./parse.py -rust $(EXTENSIONS) .PHONY : clean @@ -39,3 +42,8 @@ clean: install: c set -e; for FILE in $(INSTALL_HEADER_FILES); do cp -f encoding.out.h $$FILE; done +.PHONY: instr-table.tex +instr-table.tex: latex + +.PHONY: priv-instr-table.tex +priv-instr-table.tex: latex -- cgit v1.1 From 738fa4a5695edd54bede848f103f5d69fb5bdc6c Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Mon, 2 May 2022 18:16:29 +0530 Subject: adding python dependencies to requirements.txt --- README.md | 16 ++++++++++++---- requirements.txt | 1 + 2 files changed, 13 insertions(+), 4 deletions(-) create mode 100644 requirements.txt diff --git a/README.md b/README.md index 26d39fc..0df0cba 100644 --- a/README.md +++ b/README.md @@ -57,7 +57,7 @@ Instruction syntaxes used in this project are broadly categorized into three: - *single bit assignment* : here the value of a single bit is assigned using syntax `=`. For e.g. `6=1` means bit 6 should be 1. Here the value must be 1 or 0. - *range assignment*: here a range of bits is assigned a value using syntax: `..=`. For e.g. `31..24=0xab`. The value here can be either unsigned integer, hex (0x) or binary (0b). -- **pseudo\_instructions** (a.k.a pseudo\_ops) - These are instructions which are aliases of regular instructions. Their encodings force +- **pseudo_instructions** (a.k.a pseudo\_ops) - These are instructions which are aliases of regular instructions. Their encodings force certain restrictions over the regular instruction. The syntax for such instructions uses the `$pseudo_op` keyword as follows: ``` $pseudo_op :: @@ -77,7 +77,7 @@ Instruction syntaxes used in this project are broadly categorized into three: instruction, as this avoids existence of overlapping opcodes for users who are experimenting with unratified extensions as well. -- **imported\_instructions** - these are instructions which are borrowed from an extension into a new/different extension/sub-extension. Only regular instructions can be imported. Pseudo-op instructions cannot be imported. Example: +- **imported_instructions** - these are instructions which are borrowed from an extension into a new/different extension/sub-extension. Only regular instructions can be imported. Pseudo-op instructions cannot be imported. Example: ``` $import rv32_zkne::aes32esmi ``` @@ -116,15 +116,23 @@ of extensions are being processed such that the *base-instruction* is not includ The following artifacts can be generated using parse.py: - instr\_dict.yaml : This is file generated always by parse.py and contains the - entire main dictionary `instr_dict` in YAML format. Note, in this yaml the + entire main dictionary `instr\_dict` in YAML format. Note, in this yaml the *dots* in an instruction are replaced with *underscores* -- encoding.h : this is the header file that is used by tools like spike, pk, etc +- encoding.out.h : this is the header file that is used by tools like spike, pk, etc - instr-table.tex : the latex table of instructions used in the riscv-unpriv spec - priv-instr-table.tex : the latex table of instruction used in the riscv-priv spec - inst.chisel : chisel code to decode instructions - inst.sverilog : system verilog code to decode instructions - inst.rs : rust code containing mask and match variables for all instructions +Make sure you install the required python pre-requisites are installed by executing the following +command: + +``` +sudo apt-get install python-pip3 +pip3 install -r requirements.txt +``` + To generate all the above artifacts for all instructions currently checked in, simply run `make` from the root-directory. This should print the following log on the command-line: ``` diff --git a/requirements.txt b/requirements.txt new file mode 100644 index 0000000..c3726e8 --- /dev/null +++ b/requirements.txt @@ -0,0 +1 @@ +pyyaml -- cgit v1.1 From bc92b799d9e96b53a0e57e738bff8f12e6e1fc2d Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Mon, 2 May 2022 18:28:53 +0530 Subject: adding support for spinalhdl code generation --- .gitignore | 3 +-- Makefile | 6 +++++- README.md | 1 + parse.py | 16 +++++++++++++--- 4 files changed, 20 insertions(+), 6 deletions(-) diff --git a/.gitignore b/.gitignore index 406d882..b0ae6e9 100644 --- a/.gitignore +++ b/.gitignore @@ -5,9 +5,8 @@ inst.go instr-table.tex priv-instr-table.tex inst.rs - +inst.spinalhdl inst.sverilog - instr_dict.yaml __pycache__/ diff --git a/Makefile b/Makefile index b8cd4db..be917b4 100644 --- a/Makefile +++ b/Makefile @@ -12,7 +12,7 @@ install: everything .PHONY : everything everything: - @./parse.py -c -chisel -sverilog -rust -latex $(EXTENSIONS) + @./parse.py -c -chisel -sverilog -rust -latex -spinalhdl $(EXTENSIONS) .PHONY : encoding.out.h encoding.out.h: @@ -47,3 +47,7 @@ instr-table.tex: latex .PHONY: priv-instr-table.tex priv-instr-table.tex: latex + +.PHONY: inst.spinalhdl +inst.spinalhdl: + @./parse.py -spinalhdl $(EXTENSIONS) diff --git a/README.md b/README.md index 0df0cba..d65b0c7 100644 --- a/README.md +++ b/README.md @@ -124,6 +124,7 @@ The following artifacts can be generated using parse.py: - inst.chisel : chisel code to decode instructions - inst.sverilog : system verilog code to decode instructions - inst.rs : rust code containing mask and match variables for all instructions +- inst.spinalhdl : spinalhdl code to decode instructions Make sure you install the required python pre-requisites are installed by executing the following command: diff --git a/parse.py b/parse.py index 4ae4a51..11eb4c0 100755 --- a/parse.py +++ b/parse.py @@ -706,13 +706,16 @@ def make_ext_latex_table(type_list, dataset, latex_file, ilen, caption): latex_file.write(header+content+endtable) -def make_chisel(instr_dict): +def make_chisel(instr_dict, spinal_hdl=False): chisel_names='' cause_names_str='' csr_names_str = '' for i in instr_dict: - chisel_names += f' def {i.upper().replace(".","_"):<18s} = BitPat("b{instr_dict[i]["encoding"].replace("-","?")}")\n' + if spinal_hdl: + chisel_names += f' def {i.upper().replace(".","_"):<18s} = M"b{instr_dict[i]["encoding"].replace("-","-")}"\n' + else: + chisel_names += f' def {i.upper().replace(".","_"):<18s} = BitPat("b{instr_dict[i]["encoding"].replace("-","?")}")\n' for num, name in causes: cause_names_str += f' val {name.lower().replace(" ","_")} = {hex(num)}\n' cause_names_str += ''' val all = { @@ -740,7 +743,10 @@ def make_chisel(instr_dict): csr_names_str += ''' res.toArray }''' - chisel_file = open('inst.chisel','w') + if spinal_hdl: + chisel_file = open('inst.spinalhdl','w') + else: + chisel_file = open('inst.chisel','w') chisel_file.write(f''' /* Automatically generated by parse_opcodes */ object Instructions {{ @@ -857,6 +863,10 @@ if __name__ == "__main__": if '-chisel' in sys.argv[1:]: make_chisel(instr_dict) logging.info('inst.chisel generated successfully') + + if '-spinalhdl' in sys.argv[1:]: + make_chisel(instr_dict, True) + logging.info('inst.spinalhdl generated successfully') if '-sverilog' in sys.argv[1:]: make_sverilog(instr_dict) -- cgit v1.1