From 1d2c34a6423f262f2056e3f2e4119121cf1fd3a1 Mon Sep 17 00:00:00 2001
From: Atul Khare <atulkhare@rivosinc.com>
Date: Mon, 5 Jun 2023 15:22:29 -0700
Subject: Add Smcsrind/Sscsrind CSRs

Adds mireg2 (0x352), mireg3 (0x353), mireg4 (0x355), mireg5 (0x356),
mireg6 (0x357), sireg2 (0x152), sireg3 (0x153), sireg4 (0x155), sireg5
(0x156), sireg6 (0x157), vsireg2 (0x252), vsireg3 (0x253), vsireg4
(0x255), vsireg5 (0x256), vireg6 (0x257).
---
 constants.py | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/constants.py b/constants.py
index 8d9352f..98c4b7c 100644
--- a/constants.py
+++ b/constants.py
@@ -116,6 +116,11 @@ csrs = [
   (0x14D, 'stimecmp'), # Sstc
   (0x150, 'siselect'),
   (0x151, 'sireg'),
+  (0x152, 'sireg2'),
+  (0x153, 'sireg3'),
+  (0x155, 'sireg4'),
+  (0x156, 'sireg5'),
+  (0x157, 'sireg6'),
   (0x15C, 'stopei'),
   (0x180, 'satp'),
   (0x5A8, 'scontext'),
@@ -132,6 +137,11 @@ csrs = [
   (0x24D, 'vstimecmp'), # Sstc
   (0x250, 'vsiselect'),
   (0x251, 'vsireg'),
+  (0x252, 'vsireg2'),
+  (0x253, 'vsireg3'),
+  (0x255, 'vsireg4'),
+  (0x256, 'vsireg5'),
+  (0x257, 'vsireg6'),
   (0x25C, 'vstopei'),
   (0x280, 'vsatp'),
   (0x600, 'hstatus'),
@@ -207,6 +217,11 @@ csrs = [
   (0x34b, 'mtval2'),
   (0x350, 'miselect'),
   (0x351, 'mireg'),
+  (0x352, 'mireg2'),
+  (0x353, 'mireg3'),
+  (0x355, 'mireg4'),
+  (0x356, 'mireg5'),
+  (0x357, 'mireg6'),
   (0x35c, 'mtopei'),
   (0x3a0, 'pmpcfg0'),
   (0x3a1, 'pmpcfg1'),
-- 
cgit v1.1