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AgeCommit message (Expand)AuthorFilesLines
2012-03-13opcodes cleanupYunsup Lee1-7/+6
2012-03-10slight change to vector supervisor instructionsYunsup Lee1-4/+4
2012-03-03new instructions to handle vector exceptionsYunsup Lee1-0/+6
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+380
2011-06-19Renamed packagesAndrew Waterman1-380/+0
2011-05-15[opcodes,pk,sim,xcc] resolve a conflictYunsup Lee1-6/+6
2011-05-15[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec instsYunsup Lee1-89/+107
2011-05-13tweaked encoding of rdcycle & cousinsAndrew Waterman1-5/+8
2011-05-06[opcodes] reordered RVC instructionsAndrew Waterman1-13/+14
2011-04-24[xcc,sim,opcodes] added c.addiwAndrew Waterman1-0/+2
2011-04-24[xcc,sim,opcodes] added more RVC instructionsAndrew Waterman1-4/+26
2011-04-18[xcc,sim,opcodes] added rvc conditional branchesAndrew Waterman1-12/+14
2011-04-12[xcc,pk,sim] added privileged cflush instructionAndrew Waterman1-0/+1
2011-04-12[xcc,sim] rvc loads and storesAndrew Waterman1-4/+12
2011-04-11[xcc,sim,opcodes] more rvc instructions and bug fixesAndrew Waterman1-2/+4
2011-04-09[xcc, sim] added rvc insn c.li; misc fixesAndrew Waterman1-1/+2
2011-04-09[xcc,pk,sim,opcodes] added first RVC instructionAndrew Waterman1-5/+6
2011-04-06[opcodes,pk,sim,xcc] fix utidx - add rdYunsup Lee1-1/+1
2011-04-05[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem in...Yunsup Lee1-43/+113
2011-04-04[opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)Yunsup Lee1-0/+6
2011-04-04[opcodes,pk,sim,xcc] add vector mem instructionsYunsup Lee1-0/+38
2011-04-04[opcodes,pk,sim,xcc] add stop,utidx instructionsYunsup Lee1-0/+2
2011-04-04[opcodes,pk,sim,xcc] add fence instructions for vector unitYunsup Lee1-2/+6
2011-03-25[opcodes] minor opcode changesAndrew Waterman1-17/+17
2011-03-25[sim,pk,xcc,opcodes] removed fminmag/fmaxmagAndrew Waterman1-4/+0
2011-03-25[xcc,pk,opcodes,sim] updated encoding/insn namesAndrew Waterman1-34/+46
2011-02-15[xcc,opcodes,pk,sim] krste's re-renaming spreeAndrew Waterman1-41/+41
2011-02-15[xcc,sim,opcodes] removed mtflh/mffl/mffhAndrew Waterman1-3/+0
2011-02-02[sim,xcc,opcodes] added back mtflh.dAndrew Waterman1-1/+2
2011-02-02[opcodes,pk,sim,xcc] synci now bombs whole icacheAndrew Waterman1-1/+1
2011-02-01[xcc,opcodes,pk,sim] cleanup to FP ISAAndrew Waterman1-27/+26
2011-01-25[sim,opcodes] add mulhsu instructionAndrew Waterman1-1/+2
2011-01-25[opcodes,pk,sim,xcc] great renumbering of 2011, part deuxAndrew Waterman1-180/+177
2011-01-20[sim, pk, xcc, opcodes] great instruction renaming of 2011Andrew Waterman1-89/+92
2011-01-18[opcodes, sim, xcc] made *w insns illegal in RV32Andrew Waterman1-2/+0
2011-01-17[opcodes, pk, sim, xcc] removed nor, normalized macros to addiAndrew Waterman1-1/+0
2011-01-03[opcodes,pk,sim,xcc] flip fields to favor little endianYunsup Lee1-182/+180
2010-11-21[opcodes, pk, sim, xcc] Tweaked FP encodingAndrew Waterman1-70/+37
2010-11-21[opcodes] generate latex and verilog correctlyAndrew Waterman1-10/+10
2010-11-21[xcc, sim, pk, opcodes] new instruction encoding!Andrew Waterman1-212/+215
2010-11-21[opcodes, pk, sim, xcc] made jumps shorter and PC-relativeAndrew Waterman1-2/+2
2010-10-31[opcodes] add latex table for rm stuffYunsup Lee1-36/+36
2010-10-25[sim,xcc,pk,opcodes] static rounding modes for FP insnsAndrew Waterman1-20/+52
2010-10-07[xcc] modified opcodes for better FP decode mappingAndrew Waterman1-7/+7
2010-10-05[opcodes] added code field back to syscall/breakAndrew Waterman1-2/+2
2010-10-02[xcc, sim] mff now uses rs2 for dataAndrew Waterman1-43/+43
2010-09-28[opcodes, sim, xcc] added mffl.d instructionAndrew Waterman1-64/+66
2010-09-20[xcc, sim] changed instruction format so imm12 subs for rs2Andrew Waterman1-172/+172
2010-09-13[xcc, sim] replaced ble/bleu with bge/bgeuAndrew Waterman1-4/+4
2010-09-12[sim] renamed sllv to sll (same for other shifts)Andrew Waterman1-6/+6
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