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AgeCommit message (Expand)AuthorFilesLines
2013-07-26tweaksYunsup Lee2-76/+100
2013-07-26Factor out Hwacha/RVC and rename MFTX/MXTF to FMVAndrew Waterman7-326/+203
2013-07-25Refactor parse-opcodesAndrew Waterman4-1411/+924
2013-07-25Remove JALR static hintsAndrew Waterman1-3/+1
2013-07-23Remove CFLUSHAndrew Waterman1-1/+0
2013-04-17add auipc, lr, scAndrew Waterman5-13/+58
2012-03-24new supervisor modeAndrew Waterman2-32/+30
2012-03-18change vector fence names/encodingAndrew Waterman4-34/+10
2012-03-18clean up vector exception instructionsYunsup Lee2-14/+19
2012-03-13add more instructions for vector exception handlingYunsup Lee2-2/+9
2012-03-13add vvcfg,vtcfgYunsup Lee2-0/+4
2012-03-13opcodes cleanupYunsup Lee3-14/+12
2012-03-10slight change to vector supervisor instructionsYunsup Lee2-8/+8
2012-03-03new instructions to handle vector exceptionsYunsup Lee3-2/+14
2011-06-19temporary undoing of renamingAndrew Waterman5-0/+3585
2011-06-19Renamed packagesAndrew Waterman5-3585/+0
2011-06-19[riscv-isa-run] code cleanup; added READMEAndrew Waterman4-9/+27
2011-06-10[sim, opcodes] made sim more decoupled from opcodesAndrew Waterman2-60/+6
2011-05-29[sim,opcodes] improved sim build and run performanceAndrew Waterman2-47/+60
2011-05-18[opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)Yunsup Lee1-2/+2
2011-05-15[opcodes,pk,sim,xcc] resolve a conflictYunsup Lee3-16/+16
2011-05-15[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec instsYunsup Lee4-163/+251
2011-05-13tweaked encoding of rdcycle & cousinsAndrew Waterman3-14/+50
2011-05-06[opcodes] reordered RVC instructionsAndrew Waterman2-20/+21
2011-04-24[xcc,sim,opcodes] added c.addiwAndrew Waterman3-26/+4
2011-04-24[xcc,sim,opcodes] added more RVC instructionsAndrew Waterman3-5/+47
2011-04-18[xcc,sim,opcodes] added rvc conditional branchesAndrew Waterman2-12/+16
2011-04-12[xcc,pk,sim] added privileged cflush instructionAndrew Waterman2-0/+2
2011-04-12[xcc,sim] rvc loads and storesAndrew Waterman3-4/+24
2011-04-11[xcc,sim,opcodes] more rvc instructions and bug fixesAndrew Waterman3-3/+10
2011-04-09[xcc, sim] added rvc insn c.li; misc fixesAndrew Waterman3-2/+8
2011-04-09[xcc,pk,sim,opcodes] added first RVC instructionAndrew Waterman3-12/+16
2011-04-07[pk,sim] fixed parse-opcodes bugAndrew Waterman1-2/+2
2011-04-06[opcodes,pk,sim,xcc] fix utidx - add rdYunsup Lee3-4/+4
2011-04-05[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem in...Yunsup Lee3-92/+199
2011-04-04[opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)Yunsup Lee3-0/+12
2011-04-04[opcodes,pk,sim,xcc] add vector mem instructionsYunsup Lee3-0/+70
2011-04-04[opcodes,pk,sim,xcc] add stop,utidx instructionsYunsup Lee3-0/+24
2011-04-04[opcodes,pk,sim,xcc] add fence instructions for vector unitYunsup Lee3-2/+46
2011-03-25[opcodes] fixed up instruction tableAndrew Waterman2-1475/+1474
2011-03-25[opcodes] minor opcode changesAndrew Waterman2-58/+58
2011-03-25[sim,pk,xcc,opcodes] removed fminmag/fmaxmagAndrew Waterman2-8/+0
2011-03-25[xcc,pk,opcodes,sim] updated encoding/insn namesAndrew Waterman4-78/+181
2011-02-15[xcc,opcodes,pk,sim] krste's re-renaming spreeAndrew Waterman3-158/+124
2011-02-15[xcc,sim,opcodes] removed mtflh/mffl/mffhAndrew Waterman3-60/+0
2011-02-02[sim,xcc,opcodes] added back mtflh.dAndrew Waterman3-6/+26
2011-02-02[opcodes,pk,sim,xcc] synci now bombs whole icacheAndrew Waterman3-11/+11
2011-02-01[xcc,opcodes,pk,sim] cleanup to FP ISAAndrew Waterman3-84/+64
2011-01-31[opcodes] fixed verilog generation for shiftsAndrew Waterman2-9/+9
2011-01-25[sim,opcodes] add mulhsu instructionAndrew Waterman3-2/+13
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