diff options
| -rw-r--r-- | constants.py | 7 | ||||
| -rw-r--r-- | encoding.h | 8 | ||||
| -rw-r--r-- | unratified/rv_c_zicfiss | 5 | ||||
| -rw-r--r-- | unratified/rv_zicfiss | 14 |
4 files changed, 34 insertions, 0 deletions
diff --git a/constants.py b/constants.py index 1298aa7..0f4e777 100644 --- a/constants.py +++ b/constants.py @@ -165,8 +165,10 @@ emitted_pseudo_ops = [ 'srli_rv32', 'umax32', 'c_mop_1', + 'c_sspush_x1', 'c_mop_3', 'c_mop_5', + 'c_sspopchk_x5', 'c_mop_7', 'c_mop_9', 'c_mop_11', @@ -201,6 +203,9 @@ emitted_pseudo_ops = [ 'mop_r_26', 'mop_r_27', 'mop_r_28', + 'sspopchk_x1', + 'sspopchk_x5', + 'ssrdp', 'mop_r_29', 'mop_r_30', 'mop_r_31', @@ -213,4 +218,6 @@ emitted_pseudo_ops = [ 'mop_rr_5', 'mop_rr_6', 'mop_rr_7', + 'sspush_x1', + 'sspush_x5', ] @@ -20,6 +20,7 @@ #define MSTATUS_TVM 0x00100000 #define MSTATUS_TW 0x00200000 #define MSTATUS_TSR 0x00400000 +#define MSTATUS_SPELP 0x00800000 #define MSTATUS32_SD 0x80000000 #define MSTATUS_UXL 0x0000000300000000 #define MSTATUS_SXL 0x0000000C00000000 @@ -27,6 +28,7 @@ #define MSTATUS_MBE 0x0000002000000000 #define MSTATUS_GVA 0x0000004000000000 #define MSTATUS_MPV 0x0000008000000000 +#define MSTATUS_MPELP 0x0000020000000000 #define MSTATUS64_SD 0x8000000000000000 #define MSTATUSH_SBE 0x00000010 @@ -45,6 +47,7 @@ #define SSTATUS_XS 0x00018000 #define SSTATUS_SUM 0x00040000 #define SSTATUS_MXR 0x00080000 +#define SSTATUS_SPELP 0x00800000 #define SSTATUS32_SD 0x80000000 #define SSTATUS_UXL 0x0000000300000000 #define SSTATUS64_SD 0x8000000000000000 @@ -70,6 +73,7 @@ #define DCSR_XDEBUGVER (3U<<30) #define DCSR_NDRESET (1<<29) #define DCSR_FULLRESET (1<<28) +#define DCSR_PELP (1<<18) #define DCSR_EBREAKM (1<<15) #define DCSR_EBREAKH (1<<14) #define DCSR_EBREAKS (1<<13) @@ -148,6 +152,7 @@ #define SIP_STIP MIP_STIP #define MENVCFG_FIOM 0x00000001 +#define MENVCFG_LPE 0x00000004 #define MENVCFG_SSE 0x00000008 #define MENVCFG_CBIE 0x00000030 #define MENVCFG_CBCFE 0x00000040 @@ -187,6 +192,7 @@ #define MHPMEVENTH_OF 0x80000000 #define HENVCFG_FIOM 0x00000001 +#define HENVCFG_LPE 0x00000004 #define HENVCFG_SSE 0x00000008 #define HENVCFG_CBIE 0x00000030 #define HENVCFG_CBCFE 0x00000040 @@ -223,6 +229,7 @@ #define HSTATEENH_SSTATEEN 0x80000000 #define SENVCFG_FIOM 0x00000001 +#define SENVCFG_LPE 0x00000004 #define SENVCFG_SSE 0x00000008 #define SENVCFG_CBIE 0x00000030 #define SENVCFG_CBCFE 0x00000040 @@ -237,6 +244,7 @@ #define MSECCFG_RLB 0x00000004 #define MSECCFG_USEED 0x00000100 #define MSECCFG_SSEED 0x00000200 +#define MSECCFG_MLPE 0x00000400 /* jvt fields */ #define JVT_MODE 0x3F diff --git a/unratified/rv_c_zicfiss b/unratified/rv_c_zicfiss new file mode 100644 index 0000000..83431c6 --- /dev/null +++ b/unratified/rv_c_zicfiss @@ -0,0 +1,5 @@ +# c.sspush x1 -> c.mop.1 +$pseudo_op rv_zcmop::c.mop.N c.sspush.x1 1..0=1 6..2=0 11..7=1 12=0 15..13=3 + +# c.sspopchk x5 -> c.mop.5 +$pseudo_op rv_zcmop::c.mop.N c.sspopchk.x5 1..0=1 6..2=0 11..7=5 12=0 15..13=3 diff --git a/unratified/rv_zicfiss b/unratified/rv_zicfiss new file mode 100644 index 0000000..e46b64d --- /dev/null +++ b/unratified/rv_zicfiss @@ -0,0 +1,14 @@ +ssamoswap.w rd rs1 rs2 aq rl 31..29=2 28..27=1 14..12=2 6..2=0x0B 1..0=3 +ssamoswap.d rd rs1 rs2 aq rl 31..29=2 28..27=1 14..12=3 6..2=0x0B 1..0=3 + +# sspopchk x1/x5 -> mop.r.28 rd=x0, rs1=x1/x5 +$pseudo_op rv_zimop::mop.r.N sspopchk.x1 30=1 27=1 26=1 21=0 20=0 31=1 29..28=0 25..22=7 19..15=1 14..12=4 11..7=0 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N sspopchk.x5 30=1 27=1 26=1 21=0 20=0 31=1 29..28=0 25..22=7 19..15=5 14..12=4 11..7=0 6..2=0x1C 1..0=3 + +# ssrdp rd != x0 -> mop.r.28 rd!=x0, rs1=x0 +$pseudo_op rv_zimop::mop.r.N ssrdp rd_n0 30=1 27=1 26=1 21=0 20=0 31=1 29..28=0 25..22=7 19..15=0 14..12=4 6..2=0x1C 1..0=3 + +# sspush x1/x5 -> mop.rr.7 rd=x0, rs2=x1/x5, rs1=x0 +$pseudo_op rv_zimop::mop.rr.N sspush.x1 30=1 27=1 26=1 31=1 29..28=0 25=1 24..20=1 19..15=0 14..12=4 11..7=0 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.rr.N sspush.x5 30=1 27=1 26=1 31=1 29..28=0 25=1 24..20=5 19..15=0 14..12=4 11..7=0 6..2=0x1C 1..0=3 + |