diff options
-rw-r--r-- | Makefile | 5 | ||||
-rw-r--r-- | encoding.h | 103 | ||||
-rw-r--r-- | inst.chisel | 120 | ||||
-rw-r--r-- | opcodes | 22 | ||||
-rwxr-xr-x | parse-opcodes | 80 |
5 files changed, 206 insertions, 124 deletions
@@ -3,15 +3,16 @@ SHELL := /bin/sh ISASIM_H := ../riscv-isa-sim/riscv/encoding.h ISASIM_HWACHA_H := ../riscv-isa-sim/hwacha/opcodes_hwacha_ut.h PK_H := ../riscv-pk/pk/encoding.h +FESVR_H := ../riscv-fesvr/fesvr/encoding.h ENV_H := ../riscv-tests/env/encoding.h GAS_H := ../riscv-gnu-toolchain/binutils/include/opcode/riscv-opc.h XCC_H := ../riscv-gnu-toolchain/gcc/gcc/config/riscv/riscv-opc.h ALL_OPCODES := opcodes opcodes-pseudo opcodes-rvc opcodes-hwacha opcodes-hwacha-pseudo opcodes-hwacha-ut opcodes-custom -install: $(ISASIM_H) $(PK_H) $(ENV_H) $(GAS_H) $(XCC_H) inst.chisel instr-table.tex +install: $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) $(GAS_H) $(XCC_H) inst.chisel instr-table.tex -$(ISASIM_H) $(PK_H) $(ENV_H): $(ALL_OPCODES) parse-opcodes +$(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H): $(ALL_OPCODES) parse-opcodes cp encoding.h $@ cat opcodes | ./parse-opcodes -c >> $@ @@ -3,25 +3,61 @@ #ifndef RISCV_CSR_ENCODING_H #define RISCV_CSR_ENCODING_H -#define SR_S 0x00000001 -#define SR_PS 0x00000002 -#define SR_EI 0x00000004 -#define SR_PEI 0x00000008 -#define SR_EF 0x00000010 -#define SR_U64 0x00000020 -#define SR_S64 0x00000040 -#define SR_VM 0x00000080 -#define SR_EA 0x00000100 -#define SR_IM 0x00FF0000 -#define SR_IP 0xFF000000 -#define SR_ZERO ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EA|SR_IM|SR_IP) -#define SR_IM_SHIFT 16 -#define SR_IP_SHIFT 24 - -#define IRQ_COP 2 -#define IRQ_IPI 5 -#define IRQ_HOST 6 -#define IRQ_TIMER 7 +#define MSTATUS_SSIP 0x00000002 +#define MSTATUS_HSIP 0x00000004 +#define MSTATUS_MSIP 0x00000008 +#define MSTATUS_IE 0x00000010 +#define MSTATUS_PRV 0x00000060 +#define MSTATUS_IE1 0x00000080 +#define MSTATUS_PRV1 0x00000300 +#define MSTATUS_IE2 0x00000400 +#define MSTATUS_PRV2 0x00001800 +#define MSTATUS_IE3 0x00002000 +#define MSTATUS_PRV3 0x0000C000 +#define MSTATUS_MPRV 0x00030000 +#define MSTATUS_VM 0x00780000 +#define MSTATUS_STIE 0x01000000 +#define MSTATUS_HTIE 0x02000000 +#define MSTATUS_MTIE 0x04000000 +#define MSTATUS_FS 0x18000000 +#define MSTATUS_XS 0x60000000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS64_UA 0x0000000F00000000 +#define MSTATUS64_SA 0x000000F000000000 +#define MSTATUS64_HA 0x00000F0000000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_SIP 0x00000002 +#define SSTATUS_IE 0x00000010 +#define SSTATUS_PIE 0x00000080 +#define SSTATUS_PS 0x00000100 +#define SSTATUS_UA 0x000F0000 +#define SSTATUS_TIE 0x01000000 +#define SSTATUS_TIP 0x04000000 +#define SSTATUS_FS 0x18000000 +#define SSTATUS_XS 0x60000000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define VM_MBARE 0 +#define VM_MBB 1 +#define VM_MBBID 2 +#define VM_SV32 4 +#define VM_SV43 5 + +#define UA_RV32 0 +#define UA_RV64 4 +#define UA_RV128 8 + +#define IRQ_TIMER 0 +#define IRQ_IPI 1 +#define IRQ_HOST 2 +#define IRQ_COP 3 #define IMPL_SPIKE 1 #define IMPL_ROCKET 2 @@ -41,9 +77,16 @@ #ifdef __riscv #ifdef __riscv64 +# define MSTATUS_UA MSTATUS64_UA +# define MSTATUS_SA MSTATUS64_SA +# define MSTATUS_HA MSTATUS64_HA +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD # define RISCV_PGLEVELS 3 # define RISCV_PGSHIFT 13 #else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD # define RISCV_PGLEVELS 2 # define RISCV_PGSHIFT 12 #endif @@ -52,7 +95,9 @@ #ifndef __ASSEMBLER__ -#define read_csr(reg) ({ long __tmp; \ +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ __tmp; }) @@ -63,31 +108,25 @@ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ __tmp; }) -#define set_csr(reg, bit) ({ long __tmp; \ +#define set_csr(reg, bit) ({ unsigned long __tmp; \ if (__builtin_constant_p(bit) && (bit) < 32) \ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ else \ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ __tmp; }) -#define clear_csr(reg, bit) ({ long __tmp; \ +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ if (__builtin_constant_p(bit) && (bit) < 32) \ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ else \ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ __tmp; }) -#define rdtime() ({ unsigned long __tmp; \ - asm volatile ("rdtime %0" : "=r"(__tmp)); \ - __tmp; }) - -#define rdcycle() ({ unsigned long __tmp; \ - asm volatile ("rdcycle %0" : "=r"(__tmp)); \ - __tmp; }) +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) -#define rdinstret() ({ unsigned long __tmp; \ - asm volatile ("rdinstret %0" : "=r"(__tmp)); \ - __tmp; }) +#endif #endif diff --git a/inst.chisel b/inst.chisel index b9454d3..a4f876b 100644 --- a/inst.chisel +++ b/inst.chisel @@ -88,7 +88,11 @@ object Instructions { def SC_D = Bits("b00011????????????011?????0101111") def SCALL = Bits("b00000000000000000000000001110011") def SBREAK = Bits("b00000000000100000000000001110011") - def SRET = Bits("b10000000000000000000000001110011") + def SRET = Bits("b00010000001000000000000001110011") + def SFENCE_VM = Bits("b000100000100?????000000001110011") + def MCALL = Bits("b00100000000000000000000001110011") + def MRET = Bits("b00110000001000000000000001110011") + def MRTS = Bits("b00110000100100000000000001110011") def CSRRW = Bits("b?????????????????001?????1110011") def CSRRS = Bits("b?????????????????010?????1110011") def CSRRC = Bits("b?????????????????011?????1110011") @@ -186,29 +190,27 @@ object Causes { val misaligned_fetch = 0x0 val fault_fetch = 0x1 val illegal_instruction = 0x2 - val privileged_instruction = 0x3 - val fp_disabled = 0x4 - val syscall = 0x6 + val scall = 0x4 + val hcall = 0x5 + val mcall = 0x6 val breakpoint = 0x7 val misaligned_load = 0x8 - val misaligned_store = 0x9 - val fault_load = 0xa + val fault_load = 0x9 + val misaligned_store = 0xa val fault_store = 0xb - val accelerator_disabled = 0xc val all = { val res = collection.mutable.ArrayBuffer[Int]() res += misaligned_fetch res += fault_fetch res += illegal_instruction - res += privileged_instruction - res += fp_disabled - res += syscall + res += scall + res += hcall + res += mcall res += breakpoint res += misaligned_load - res += misaligned_store res += fault_load + res += misaligned_store res += fault_store - res += accelerator_disabled res.toArray } } @@ -216,29 +218,10 @@ object CSRs { val fflags = 0x1 val frm = 0x2 val fcsr = 0x3 - val stats = 0xc0 - val sup0 = 0x500 - val sup1 = 0x501 - val epc = 0x502 - val badvaddr = 0x503 - val ptbr = 0x504 - val asid = 0x505 - val count = 0x506 - val compare = 0x507 - val evec = 0x508 - val cause = 0x509 - val status = 0x50a - val hartid = 0x50b - val impl = 0x50c - val fatc = 0x50d - val send_ipi = 0x50e - val clear_ipi = 0x50f - val reset = 0x51d - val tohost = 0x51e - val fromhost = 0x51f val cycle = 0xc00 val time = 0xc01 val instret = 0xc02 + val stats = 0xc0 val uarch0 = 0xcc0 val uarch1 = 0xcc1 val uarch2 = 0xcc2 @@ -255,38 +238,43 @@ object CSRs { val uarch13 = 0xccd val uarch14 = 0xcce val uarch15 = 0xccf - val counth = 0x586 + val sstatus = 0x100 + val stvec = 0x101 + val stimecmp = 0x121 + val sscratch = 0x140 + val sepc = 0x141 + val sptbr = 0x188 + val sasid = 0x189 + val scycle = 0x900 + val stime = 0x901 + val sinstret = 0x902 + val scause = 0xd40 + val sbadaddr = 0xd41 + val mstatus = 0x300 + val mscratch = 0x340 + val mepc = 0x341 + val mcause = 0x342 + val mbadaddr = 0x343 + val reset = 0x780 + val tohost = 0x781 + val fromhost = 0x782 + val send_ipi = 0x783 + val hartid = 0xfc0 val cycleh = 0xc80 val timeh = 0xc81 val instreth = 0xc82 + val scycleh = 0x980 + val stimeh = 0x981 + val sinstreth = 0x982 val all = { val res = collection.mutable.ArrayBuffer[Int]() res += fflags res += frm res += fcsr - res += stats - res += sup0 - res += sup1 - res += epc - res += badvaddr - res += ptbr - res += asid - res += count - res += compare - res += evec - res += cause - res += status - res += hartid - res += impl - res += fatc - res += send_ipi - res += clear_ipi - res += reset - res += tohost - res += fromhost res += cycle res += time res += instret + res += stats res += uarch0 res += uarch1 res += uarch2 @@ -303,14 +291,38 @@ object CSRs { res += uarch13 res += uarch14 res += uarch15 + res += sstatus + res += stvec + res += stimecmp + res += sscratch + res += sepc + res += sptbr + res += sasid + res += scycle + res += stime + res += sinstret + res += scause + res += sbadaddr + res += mstatus + res += mscratch + res += mepc + res += mcause + res += mbadaddr + res += reset + res += tohost + res += fromhost + res += send_ipi + res += hartid res.toArray } val all32 = { val res = collection.mutable.ArrayBuffer(all:_*) - res += counth res += cycleh res += timeh res += instreth + res += scycleh + res += stimeh + res += sinstreth res.toArray } } @@ -113,15 +113,19 @@ lr.d rd rs1 24..20=0 aqrl 31..29=0 28..27=2 14..12=3 6..2=0x0B 1..0=3 sc.d rd rs1 rs2 aqrl 31..29=0 28..27=3 14..12=3 6..2=0x0B 1..0=3 # SYSTEM -scall 11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3 -sbreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3 -sret 11..7=0 19..15=0 31..20=0x800 14..12=0 6..2=0x1C 1..0=3 -csrrw rd rs1 imm12 14..12=1 6..2=0x1C 1..0=3 -csrrs rd rs1 imm12 14..12=2 6..2=0x1C 1..0=3 -csrrc rd rs1 imm12 14..12=3 6..2=0x1C 1..0=3 -csrrwi rd rs1 imm12 14..12=5 6..2=0x1C 1..0=3 -csrrsi rd rs1 imm12 14..12=6 6..2=0x1C 1..0=3 -csrrci rd rs1 imm12 14..12=7 6..2=0x1C 1..0=3 +scall 11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3 +sbreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3 +sret 11..7=0 19..15=0 31..20=0x102 14..12=0 6..2=0x1C 1..0=3 +sfence.vm 11..7=0 rs1 31..20=0x104 14..12=0 6..2=0x1C 1..0=3 +mcall 11..7=0 19..15=0 31..20=0x200 14..12=0 6..2=0x1C 1..0=3 +mret 11..7=0 19..15=0 31..20=0x302 14..12=0 6..2=0x1C 1..0=3 +mrts 11..7=0 19..15=0 31..20=0x309 14..12=0 6..2=0x1C 1..0=3 +csrrw rd rs1 imm12 14..12=1 6..2=0x1C 1..0=3 +csrrs rd rs1 imm12 14..12=2 6..2=0x1C 1..0=3 +csrrc rd rs1 imm12 14..12=3 6..2=0x1C 1..0=3 +csrrwi rd rs1 imm12 14..12=5 6..2=0x1C 1..0=3 +csrrsi rd rs1 imm12 14..12=6 6..2=0x1C 1..0=3 +csrrci rd rs1 imm12 14..12=7 6..2=0x1C 1..0=3 # F/D EXTENSIONS fadd.s rd rs1 rs2 31..27=0x00 rm 26..25=0 6..2=0x14 1..0=3 diff --git a/parse-opcodes b/parse-opcodes index 86f8c18..72bc44a 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -45,44 +45,31 @@ causes = [ (0x00, 'misaligned fetch'), (0x01, 'fault fetch'), (0x02, 'illegal instruction'), - (0x03, 'privileged instruction'), - (0x04, 'FP disabled'), - (0x06, 'syscall'), + (0x04, 'scall'), + (0x05, 'hcall'), + (0x06, 'mcall'), (0x07, 'breakpoint'), (0x08, 'misaligned load'), - (0x09, 'misaligned store'), - (0x0A, 'fault load'), + (0x09, 'fault load'), + (0x0A, 'misaligned store'), (0x0B, 'fault store'), - (0x0C, 'accelerator disabled'), ] csrs = [ + # Standard User R/W (0x001, 'fflags'), (0x002, 'frm'), (0x003, 'fcsr'), - (0x0C0, 'stats'), # XXX - (0x500, 'sup0'), - (0x501, 'sup1'), - (0x502, 'epc'), - (0x503, 'badvaddr'), - (0x504, 'ptbr'), - (0x505, 'asid'), - (0x506, 'count'), - (0x507, 'compare'), - (0x508, 'evec'), - (0x509, 'cause'), - (0x50A, 'status'), - (0x50B, 'hartid'), - (0x50C, 'impl'), - (0x50D, 'fatc'), - (0x50E, 'send_ipi'), - (0x50F, 'clear_ipi'), - (0x51D, 'reset'), - (0x51E, 'tohost'), - (0x51F, 'fromhost'), + + # Standard User RO (0xC00, 'cycle'), (0xC01, 'time'), (0xC02, 'instret'), + + # Nonstandard User R/W + (0x0C0, 'stats'), + + # Nonstandard User RO (0xCC0, 'uarch0'), (0xCC1, 'uarch1'), (0xCC2, 'uarch2'), @@ -99,13 +86,52 @@ csrs = [ (0xCCD, 'uarch13'), (0xCCE, 'uarch14'), (0xCCF, 'uarch15'), + + # Standard Supervisor R/W + (0x100, 'sstatus'), + (0x101, 'stvec'), + (0x121, 'stimecmp'), + (0x140, 'sscratch'), + (0x141, 'sepc'), + (0x188, 'sptbr'), + (0x189, 'sasid'), + + # Standard Supervisor R/W Shadows of User RO + (0x900, 'scycle'), + (0x901, 'stime'), + (0x902, 'sinstret'), + + # Standard Supervisor RO + (0xD40, 'scause'), + (0xD41, 'sbadaddr'), + + # Standard Machine R/W + (0x300, 'mstatus'), + (0x340, 'mscratch'), + (0x341, 'mepc'), + (0x342, 'mcause'), + (0x343, 'mbadaddr'), + + # Nonstandard Machine R/W + (0x780, 'reset'), + (0x781, 'tohost'), + (0x782, 'fromhost'), + (0x783, 'send_ipi'), + + # Nonstandard Machine RO + (0xFC0, 'hartid'), ] csrs32 = [ - (0x586, 'counth'), + # Standard User RO (0xC80, 'cycleh'), (0xC81, 'timeh'), (0xC82, 'instreth'), + + # Standard Supervisor R/W Shadows of User RO + (0x980, 'scycleh'), + (0x981, 'stimeh'), + (0x982, 'sinstreth'), ] opcode_base = 0 |